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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t65sm2886736itt.12.2017.01.23.09.41.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jan 2017 09:41:27 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] coresight: etm4x: Fix enabling of cycle accurate tracing in perf. Date: Mon, 23 Jan 2017 10:41:23 -0700 Message-Id: <1485193284-31636-3-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1485193284-31636-1-git-send-email-mathieu.poirier@linaro.org> References: <1485193284-31636-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Leach Using perf record 'cyclacc' option in cs_etm event was not setting up cycle accurate trace correctly. Corrects bit set in TRCCONFIGR to enable cycle accurate trace. Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec. Signed-off-by: Mike Leach Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 031480f2c34d..f432febdda49 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) - config->cfg |= ETMv4_MODE_CYCACC; + if (attr->config & BIT(ETM_OPT_CYCACC)) { + config->cfg |= BIT(4); + /* TRM: Must program this for cycacc to work */ + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } if (attr->config & BIT(ETM_OPT_TS)) config->cfg |= ETMv4_MODE_TIMESTAMP; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index ba8d3f86de21..b3b5ea7b7fb3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -146,6 +146,7 @@ #define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF +#define ETM_CYC_THRESHOLD_DEFAULT 0x100 #define ETMv4_EVENT_MASK 0xFF #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f