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[209.132.180.67]) by mx.google.com with ESMTP id t18si5641892pfj.268.2017.01.11.04.08.17; Wed, 11 Jan 2017 04:08:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937605AbdAKMIO (ORCPT + 25 others); Wed, 11 Jan 2017 07:08:14 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:57411 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965832AbdAKMHS (ORCPT ); Wed, 11 Jan 2017 07:07:18 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v0BC7HZ1029400; Wed, 11 Jan 2017 06:07:17 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v0BC7HwQ020591; Wed, 11 Jan 2017 06:07:17 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 11 Jan 2017 06:07:16 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v0BC77KO008223; Wed, 11 Jan 2017 06:07:15 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas CC: , , , , Subject: [PATCH 3/5] PCI: dwc: dra7xx: Add support to force RC to work in GEN1 mode Date: Wed, 11 Jan 2017 17:36:53 +0530 Message-ID: <1484136415-20798-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1484136415-20798-1-git-send-email-kishon@ti.com> References: <1484136415-20798-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCIe in AM57x/DRA7x devices is by default configured to work in GEN2 mode. However there may be situations when working in GEN1 mode is desired. One example is limitation i925 (PCIe GEN2 mode not supported at junction temperatures < 0C). Add support to force Root Complex to work in GEN1 mode if so desired, but don't force GEN1 mode on any board just yet. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 1.7.9.5 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index f6d0c63..587b18c 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -63,11 +64,14 @@ #define LINK_UP BIT(16) #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF +#define EXP_CAP_ID_OFFSET 0x70 + struct dra7xx_pcie { struct pcie_port pp; void __iomem *base; /* DT ti_conf */ int phy_count; /* DT phy-names count */ struct phy **phy; + int link_gen; }; #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) @@ -96,12 +100,33 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) struct pcie_port *pp = &dra7xx->pp; struct device *dev = pp->dev; u32 reg; + u32 exp_cap_off = EXP_CAP_ID_OFFSET; if (dw_pcie_link_up(pp)) { dev_err(dev, "link is already up\n"); return 0; } + if (dra7xx->link_gen == 1) { + dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, + 4, ®); + if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { + reg &= ~((u32)PCI_EXP_LNKCAP_SLS); + reg |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCAP, 4, reg); + } + + dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, + 2, ®); + if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { + reg &= ~((u32)PCI_EXP_LNKCAP_SLS); + reg |= PCI_EXP_LNKCAP_SLS_2_5GB; + dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCTL2, 2, reg); + } + } + reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg |= LTSSM_EN; dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); @@ -397,6 +422,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) reg &= ~LTSSM_EN; dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); + dra7xx->link_gen = of_pci_get_max_link_speed(np); + if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2) + dra7xx->link_gen = 2; + ret = dra7xx_add_pcie_port(dra7xx, pdev); if (ret < 0) goto err_gpio;