From patchwork Tue Jan 3 18:10:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 89703 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp8130831qgi; Tue, 3 Jan 2017 10:11:55 -0800 (PST) X-Received: by 10.98.156.198 with SMTP id u67mr56084226pfk.109.1483467115745; Tue, 03 Jan 2017 10:11:55 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6si69792379plj.245.2017.01.03.10.11.55; Tue, 03 Jan 2017 10:11:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965281AbdACSLk (ORCPT + 25 others); Tue, 3 Jan 2017 13:11:40 -0500 Received: from foss.arm.com ([217.140.101.70]:34732 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760168AbdACSKa (ORCPT ); Tue, 3 Jan 2017 13:10:30 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 389741650; Tue, 3 Jan 2017 10:10:30 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0BFBB3F24D; Tue, 3 Jan 2017 10:10:30 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 65A021AE3C07; Tue, 3 Jan 2017 18:10:29 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: marc.zyngier@arm.com, mark.rutland@arm.com, kim.phillips@arm.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, tglx@linutronix.de, peterz@infradead.org, alexander.shishkin@linux.intel.com, robh@kernel.org, suzuki.poulose@arm.com, pawel.moll@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, linux-kernel@vger.kernel.org, Will Deacon Subject: [RFC PATCH 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 Date: Tue, 3 Jan 2017 18:10:21 +0000 Message-Id: <1483467027-14547-5-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1483467027-14547-1-git-send-email-will.deacon@arm.com> References: <1483467027-14547-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SPE architecture requires each exception level to enable access to the SPE controls for the exception level below it, since additional context-switch logic may be required to handle the buffer safely. This patch allows EL1 (host) access to the SPE controls when entered at EL2. Cc: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/kernel/head.S | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 4b1abac3485a..6a97831dcf3b 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -592,8 +592,8 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems #endif /* EL2 debug */ - mrs x0, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer - sbfx x0, x0, #8, #4 + mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer + sbfx x0, x1, #8, #4 cmp x0, #1 b.lt 4f // Skip if no PMU present mrs x0, pmcr_el0 // Disable debug access traps @@ -601,6 +601,16 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems 4: csel x0, xzr, x0, lt // all PMU counters from EL1 msr mdcr_el2, x0 // (if they exist) + /* Statistical profiling */ + ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer + cbz x0, 5f // Skip if SPE not present + mrs x0, mdcr_el2 // Preserve HPMN field + cmp x2, xzr // If VHE is not enabled, + mov x1, #3 // use EL1&0 translations, + cinc x1, x1, ne // otherwise use EL2 and + bfi x0, x1, #12, #3 // enable/disable access + msr mdcr_el2, x0 // traps accordingly. +5: /* Stage-2 translation */ msr vttbr_el2, xzr