From patchwork Fri Dec 30 09:56:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 89316 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp6367134qgi; Fri, 30 Dec 2016 01:56:44 -0800 (PST) X-Received: by 10.99.237.17 with SMTP id d17mr83410041pgi.48.1483091804649; Fri, 30 Dec 2016 01:56:44 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f17si56456250plj.199.2016.12.30.01.56.44; Fri, 30 Dec 2016 01:56:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753828AbcL3J4f (ORCPT + 25 others); Fri, 30 Dec 2016 04:56:35 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:31181 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753807AbcL3J4c (ORCPT ); Fri, 30 Dec 2016 04:56:32 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id uBU9uQgB003972; Fri, 30 Dec 2016 03:56:26 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id uBU9uQTl025936; Fri, 30 Dec 2016 03:56:26 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 30 Dec 2016 03:56:25 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id uBU9uFlb016678; Fri, 30 Dec 2016 03:56:24 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas CC: , , , , Subject: [PATCH v2 3/3] PCI: dra7xx: Enable MSI and legacy interrupts simultaneously Date: Fri, 30 Dec 2016 15:26:14 +0530 Message-ID: <1483091774-8332-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1483091774-8332-1-git-send-email-kishon@ti.com> References: <1483091774-8332-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dra7xx driver had a bug in that if CONFIG_PCI_MSI config is enabled, it doesn't support legacy interrupt. Fix it here so that both MSI and legacy interrupts can be enabled simultaneously and one of them will be used based on the connected device. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pci-dra7xx.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) -- 1.7.9.5 diff --git a/drivers/pci/controller/pci-dra7xx.c b/drivers/pci/controller/pci-dra7xx.c index 587b18c..5ee14b7 100644 --- a/drivers/pci/controller/pci-dra7xx.c +++ b/drivers/pci/controller/pci-dra7xx.c @@ -72,6 +72,7 @@ struct dra7xx_pcie { int phy_count; /* DT phy-names count */ struct phy **phy; int link_gen; + struct irq_domain *irq_domain; }; #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) @@ -143,13 +144,8 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, ~LEG_EP_INTERRUPTS & ~MSI); - if (IS_ENABLED(CONFIG_PCI_MSI)) - dra7xx_pcie_writel(dra7xx, - PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI); - else - dra7xx_pcie_writel(dra7xx, - PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, - LEG_EP_INTERRUPTS); + dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, + MSI | LEG_EP_INTERRUPTS); } static void dra7xx_pcie_host_init(struct pcie_port *pp) @@ -164,8 +160,7 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); dra7xx_pcie_establish_link(dra7xx); - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); dra7xx_pcie_enable_interrupts(dra7xx); } @@ -190,6 +185,7 @@ static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) { struct device *dev = pp->dev; + struct dra7xx_pcie *dra7xx_pcie = to_dra7xx_pcie(pp); struct device_node *node = dev->of_node; struct device_node *pcie_intc_node = of_get_next_child(node, NULL); @@ -198,9 +194,9 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) return -ENODEV; } - pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4, - &intx_domain_ops, pp); - if (!pp->irq_domain) { + dra7xx_pcie->irq_domain = irq_domain_add_linear(pcie_intc_node, 4, + &intx_domain_ops, pp); + if (!dra7xx_pcie->irq_domain) { dev_err(dev, "Failed to get a INTx IRQ domain\n"); return -ENODEV; } @@ -224,7 +220,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) case INTB: case INTC: case INTD: - generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg))); + generic_handle_irq(irq_find_mapping(dra7xx->irq_domain, + ffs(reg))); break; } @@ -310,11 +307,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, return ret; } - if (!IS_ENABLED(CONFIG_PCI_MSI)) { - ret = dra7xx_pcie_init_irq_domain(pp); - if (ret < 0) - return ret; - } + ret = dra7xx_pcie_init_irq_domain(pp); + if (ret < 0) + return ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics"); pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));