From patchwork Mon Dec 12 13:05:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 87686 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1627093qgi; Mon, 12 Dec 2016 05:06:04 -0800 (PST) X-Received: by 10.84.194.37 with SMTP id g34mr185803514pld.36.1481547964842; Mon, 12 Dec 2016 05:06:04 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q11si42581754pfc.143.2016.12.12.05.06.04; Mon, 12 Dec 2016 05:06:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752871AbcLLNGA (ORCPT + 25 others); Mon, 12 Dec 2016 08:06:00 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:37051 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752767AbcLLNF4 (ORCPT ); Mon, 12 Dec 2016 08:05:56 -0500 Received: by mail-wm0-f43.google.com with SMTP id t79so67021803wmt.0 for ; Mon, 12 Dec 2016 05:05:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xCcPEnyu9VoYp3YElWqoduaLiZ+9JmUV2m+hinJIJws=; b=VdrwjafMkt5J9E5NEqIDIv2yE+Pb8PtoWRmAtVijy2ZUXP+Xsqlz6X1ixqhJw6O1PT dMa4nwIuC0RGf0eYIu62BcO2gga2fTrgaoK/dZquBqYjeWi5Ub7Shf/XEFh/ybHguQ14 /7FsVXZ/fh8o/puV+50kxOfCK7dGIaNE3gMA2kWuctjgFlrOjcEozLy/w7NfxOW1vEJE m+DjGET+b3Z20xD2TvgflNTckcZc4O8nhQjK7gEP5i+6/nDtQ9/cySGi4wandx/z8+c8 uPpM9yNQuDtznBA9I2Afil1OBjcnSDLJBkjimfkd2crhNnH0Y6E252tldwAsDx431WjR FMIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xCcPEnyu9VoYp3YElWqoduaLiZ+9JmUV2m+hinJIJws=; b=iPIp1hs8xAqFKtIu6vzXxjYtwgFQRUxxF81KfSeB+VI5y8X/JXgjaRdZKpOUvFS2H5 X2csDMEi41Ud8m9y1YcsALxX4SfyHdHni9m55Ovfwiuzfd8RTxlbym0Dmr62ScOavWkE zAHF3mMLSgfIcW0hhOMHDd7sRdnLGIJtoZK2PIajJvLDYTI9e6/bW5ZSo4wDfKWLs/31 orBZMaWMC0nJLsOrBBVdoJjzvqO2r8PMfewLnIUZT7zaTIsBtTT662qaG4HkAMuI6JIF wKf/18MeEiu0x6m5GyoscJZNcdK9V4HIdoywq1Riu1LAEKgGvTtciCPUtm8MAdv1shgy bqxA== X-Gm-Message-State: AKaTC001NZB4iupe+9xo6Z++fu9FBa1jWUcJ6GYGb1ai5H33WHT5wQiNTP+unn4uRTMS/B4Q X-Received: by 10.28.13.144 with SMTP id 138mr8760646wmn.120.1481547954987; Mon, 12 Dec 2016 05:05:54 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id a13sm35512620wma.18.2016.12.12.05.05.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Dec 2016 05:05:54 -0800 (PST) From: Bartosz Golaszewski To: Jyri Sarha , Tomi Valkeinen , David Airlie , Kevin Hilman , Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Laurent Pinchart , Peter Ujfalusi , Russell King Cc: LKML , arm-soc , linux-drm , linux-devicetree , Bartosz Golaszewski Subject: [PATCH v6 5/5] ARM: dts: da850: specify the maximum pixel clock rate for tilcdc Date: Mon, 12 Dec 2016 14:05:42 +0100 Message-Id: <1481547942-24775-6-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1481547942-24775-1-git-send-email-bgolaszewski@baylibre.com> References: <1481547942-24775-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org At maximum CPU frequency of 300 MHz the maximum pixel clock frequency is 37.5 MHz[1]. We must filter out any mode for which the calculated pixel clock rate would exceed this value. Specify the max-pixelclock property for the display node for da850-lcdk. [1] http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_LCD_Controller_(LCDC)_Throughput_and_Optimization_Techniques Signed-off-by: Bartosz Golaszewski --- arch/arm/boot/dts/da850.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.9.3 diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 3f51e59..ba5bf80 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -452,6 +452,7 @@ compatible = "ti,da850-tilcdc"; reg = <0x213000 0x1000>; interrupts = <52>; + max-pixelclock = <37500>; status = "disabled"; }; };