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([80.215.203.217]) by smtp.gmail.com with ESMTPSA id ct7sm24062084wjc.2.2016.11.24.07.14.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Nov 2016 07:14:49 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v2 3/7] PWM: add pwm-stm32 DT bindings Date: Thu, 24 Nov 2016 16:14:19 +0100 Message-Id: <1480000463-9625-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> References: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define bindings for pwm-stm32 version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/pwm/pwm-stm32.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..36263f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,37 @@ +STMicroelectronics PWM driver bindings for STM32 + +Must be a sub-node of STM32 general purpose timer driver + +Required parameters: +- compatible: Must be "st,stm32-pwm" +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes + for PWM module. + For Pinctrl properties, please refer to [1]. + +Optional parameters: +- st,breakinput: Set if the hardware have break input capabilities +- st,breakinput-polarity: Set break input polarity. Default is 0 + The value define the active polarity: + - 0 (active LOW) + - 1 (active HIGH) +- st,pwm-num-chan: Number of available PWM channels. Default is 0. +- st,32bits-counter: Set if the hardware have a 32 bits counter +- st,complementary: Set if the hardware have complementary output channels + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + gptimer1: gptimer1@40010000 { + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm1@0 { + compatible = "st,stm32-pwm"; + st,pwm-num-chan = <4>; + st,breakinput; + st,complementary; + }; + };