From patchwork Tue Oct 25 13:52:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 79181 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp3125894qge; Tue, 25 Oct 2016 06:53:54 -0700 (PDT) X-Received: by 10.99.237.69 with SMTP id m5mr32999443pgk.113.1477403634514; Tue, 25 Oct 2016 06:53:54 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m5si15269029pgn.64.2016.10.25.06.53.53; Tue, 25 Oct 2016 06:53:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935633AbcJYNxg (ORCPT + 27 others); Tue, 25 Oct 2016 09:53:36 -0400 Received: from mail-lf0-f52.google.com ([209.85.215.52]:35036 "EHLO mail-lf0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758966AbcJYNxL (ORCPT ); Tue, 25 Oct 2016 09:53:11 -0400 Received: by mail-lf0-f52.google.com with SMTP id f134so48106705lfg.2 for ; Tue, 25 Oct 2016 06:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Q4+6Qgy7yKGWA/aDa8n+6sUJ4xy0CpoTICG7HslspWs=; b=eTcu3twMlyw6KyIF80NRZ9i+wSHBZb2w0I+3Bsczs0ZwHfKkUSQgDPnPQifMh7r1eK g3uYFwMGyGyNmeB9vPOElq9DRc91+khKWcPaIRkF+b1pKOJkEKzkJVG+tSiDxgVeIrE1 YIKAPrOGrSOVlmh4KkYs47Zp63HrGyeXQKktzIJBSqiCzXhAiveIXrd/smoA+gjhGTbF S+4Ug0zGFuIowh7MJq389klCYhMZexQRSwnL0vf1joGRhF6mxSgkQ7iwVvWSqKvx1Fr7 Hq1DxlLrcYGyH7ne+OrQ+cHIDW8XzfXS+AyvqsKZO8na+0g37P4plAWJPVAIDCHOXrEu uKuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q4+6Qgy7yKGWA/aDa8n+6sUJ4xy0CpoTICG7HslspWs=; b=kIn4XDzSFtfRgp7Dhjz6Sv7JPQdJ8tYwOVmIO3ti20JiDx1F6moXVX0g2S6A/JeY53 FzqZ3SlKhPSTLp5381DUZtpV4rsYYELWfGi9N6Rwn1rQ8rbYRHbplUGtF7OC61N186E6 H9xzREZCl/2YE3yPxu15ezLPNfpSyFCbHPnSurtt+HjEybWIbhmf0mwYY7lyyqRLqQEu TlyLZzzWNWiXT7eCISkRihSX94w8fsoNxQDaxYkqzo4kciXjTMHIPf/t1Qj0tFlBWOEW JE88DaIK4JGtVcjJxaolKNRWjOWOMoFedR8UDqcLDAo5EfmwjmybMwB8rMRoiiYzKKQS SR9Q== X-Gm-Message-State: ABUngvevvhWRs1WM+Dc7NXjU+GsWLJVJ1kPeGH3OkydxM2rhcy3FIEj3fckBS8N285NWAcai X-Received: by 10.194.201.103 with SMTP id jz7mr19222511wjc.70.1477403589258; Tue, 25 Oct 2016 06:53:09 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id v4sm3801282wmd.17.2016.10.25.06.53.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Oct 2016 06:53:08 -0700 (PDT) From: Alexandre Bailon To: khilman@baylibre.com, david@lechnology.com, b-liu@ti.com, balbi@kernel.org Cc: linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Alexandre Bailon Subject: [PATCH 2/3] phy: da8xx-usb: Configure CFGCHIP2 to support OTG workaround Date: Tue, 25 Oct 2016 15:52:55 +0200 Message-Id: <1477403576-11825-3-git-send-email-abailon@baylibre.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1477403576-11825-1-git-send-email-abailon@baylibre.com> References: <1477403576-11825-1-git-send-email-abailon@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If we configure the da8xx OTG phy in OTG mode, neither device or host mode will work. That is because the PHY is not able to detect and notify the driver that value of ID pin changed. To work despite this hardware limitation, the da8xx glue implement a workaround. But to work, the workaround require the VBUS sense and the session end comparator to enabled. Enable them if the phy is configured in OTG mode. Signed-off-by: Alexandre Bailon --- drivers/phy/phy-da8xx-usb.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) -- 2.7.3 diff --git a/drivers/phy/phy-da8xx-usb.c b/drivers/phy/phy-da8xx-usb.c index 32ae78c..fd39292 100644 --- a/drivers/phy/phy-da8xx-usb.c +++ b/drivers/phy/phy-da8xx-usb.c @@ -93,24 +93,31 @@ static int da8xx_usb20_phy_power_off(struct phy *phy) static int da8xx_usb20_phy_set_mode(struct phy *phy, enum phy_mode mode) { struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy); + int ret; u32 val; + ret = regmap_read(d_phy->regmap, CFGCHIP(2), &val); + if (ret) + return ret; + + val &= ~CFGCHIP2_OTGMODE_MASK; + switch (mode) { case PHY_MODE_USB_HOST: /* Force VBUS valid, ID = 0 */ - val = CFGCHIP2_OTGMODE_FORCE_HOST; + val |= CFGCHIP2_OTGMODE_FORCE_HOST; break; case PHY_MODE_USB_DEVICE: /* Force VBUS valid, ID = 1 */ - val = CFGCHIP2_OTGMODE_FORCE_DEVICE; + val |= CFGCHIP2_OTGMODE_FORCE_DEVICE; break; case PHY_MODE_USB_OTG: /* Don't override the VBUS/ID comparators */ - val = CFGCHIP2_OTGMODE_NO_OVERRIDE; + val |= CFGCHIP2_OTGMODE_NO_OVERRIDE | + CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN; break; default: return -EINVAL; } - regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGMODE_MASK, - val); + regmap_write(d_phy->regmap, CFGCHIP(2), val); return 0; }