From patchwork Fri Oct 21 09:08:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 78614 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp1192923qge; Fri, 21 Oct 2016 02:08:27 -0700 (PDT) X-Received: by 10.98.214.194 with SMTP id a63mr9859883pfl.9.1477040907400; Fri, 21 Oct 2016 02:08:27 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id va14si1504594pab.234.2016.10.21.02.08.27; Fri, 21 Oct 2016 02:08:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932501AbcJUJIY (ORCPT + 27 others); Fri, 21 Oct 2016 05:08:24 -0400 Received: from mail-qk0-f174.google.com ([209.85.220.174]:35797 "EHLO mail-qk0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752372AbcJUJIT (ORCPT ); Fri, 21 Oct 2016 05:08:19 -0400 Received: by mail-qk0-f174.google.com with SMTP id z190so139185931qkc.2 for ; Fri, 21 Oct 2016 02:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=yMcbQbnWiuqGFMtUKLe/SklYG6pkLYa06V5TArcq4q4=; b=dH498VutjJwRq5yp4nvnnTpL///Lj0a2WVUoK1W+HceGn0nJknUcbkvxTnCFmYxnMC 9y9Mu4HxW9tdRau+J4B4jcSUNYmTSjriZlVLXXYZ0h4MrfK9jbbRJdF7xJfD8HiN6zbt ZBnqLt609bg3Olxbk9dvNlwEM9USFXpiYXB0o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yMcbQbnWiuqGFMtUKLe/SklYG6pkLYa06V5TArcq4q4=; b=AyW/jvyWAL2aak3WIbeb4ZAOcn4Ue7aJZelqM650ejwzZw/O822pZjFD7UUt+h7uk3 ++gGAMxv9qgjSSLYWdGVBGF+/I7C5mmLPAw4DPEu1xzJclrkZIoIkV+rj2WCrnlpaktR TPJmXkMz8hHp7v7xs8MrwOox6+jgU48URuer7szargCI8oA3/pQ9WMtvZ6dNaMSOflOJ LZ+vZSAofxKqU7+ZTbL9a+slhR+ftGuhG9DkoEt/Z8dlVAx1/PuZiHdT6c/GrZawkjpV GBWFcT/o9KTiu5H3q0aOkD4ZqEShSA2eo5jgVSyYoKLIAQ40JGWI27aMS16hZlIqsLnF iUug== X-Gm-Message-State: AA6/9RkxHsha/FCJhAGlP3uHT/oFQYrERF5mqMAApQmHvEeFlqQyJl/UekY01Wbq9I6Yihhe X-Received: by 10.194.200.162 with SMTP id jt2mr3066345wjc.172.1477040898852; Fri, 21 Oct 2016 02:08:18 -0700 (PDT) Received: from localhost.localdomain (cpc89244-aztw30-2-0-cust4998.18-1.cable.virginm.net. [86.31.179.135]) by smtp.gmail.com with ESMTPSA id s133sm3095768wmd.19.2016.10.21.02.08.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 21 Oct 2016 02:08:17 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@stlinux.com, patrice.chotard@st.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org Subject: [PATCH] ARM: sti: stih407-clocks: Identify critical clocks Date: Fri, 21 Oct 2016 10:08:11 +0100 Message-Id: <1477040891-31611-1-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Lots of platforms contain clocks which if turned off would prove fatal. The only way to recover is to restart the board(s). This driver takes references to clocks which are required to be always-on. The Common Clk Framework will then take references to them. This way they will not be turned off during the clk_disabled_unused() procedure. In this patch we are identifying clocks, which if gated would render the STiH407 development board unserviceable. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-clock.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 1.9.1 Acked-by: Patrice Chotard diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 13029c0..34c119a 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -101,6 +101,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +113,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = ; }; }; @@ -126,6 +128,7 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; clk_s_c0: clockgen-c@09103000 { @@ -139,6 +142,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +198,12 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = , + , + , + , + , + ; }; };