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[209.132.180.67]) by mx.google.com with ESMTP id qi8si37784931pac.283.2016.10.20.11.56.35; Thu, 20 Oct 2016 11:56:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org; dkim=pass header.i=@codeaurora.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754995AbcJTS4Z (ORCPT + 27 others); Thu, 20 Oct 2016 14:56:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:34522 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934175AbcJTS4V (ORCPT ); Thu, 20 Oct 2016 14:56:21 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 544FE61BC6; Thu, 20 Oct 2016 18:56:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476989780; bh=3rL0e7U6EReV6lTdVRkAgdIgqQwW2AvXjnU9Fl0NS5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GUn4zcFQOuBnkk2buTX+6h7HAPAeTPrTsnZe0JJQifxRgnuxumLIvdyW+R1O/nIh3 qvFv64o69DIGB2IHaz+sDiyTNieCK3YGUf1ZoS9FJhaFzjg6akUIMxVL0oM4EBaJcn qh5jbOjWgtVnuN6LWUsKBltXszb45TQ+HP+sxoGQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,SPF_PASS,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from spjoshi-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: spjoshi@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 565D861A87; Thu, 20 Oct 2016 18:56:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1476989779; bh=3rL0e7U6EReV6lTdVRkAgdIgqQwW2AvXjnU9Fl0NS5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J5FlVs9wKv6aN5N+NLjH5jU4BnTISON0IHtnSsoAitZEH4telDJi9BWgHbx7Va6+n m/hy9sKZnRPaBL9zZ06tQIm8mTXEOBs/L7m0orrsSn3m4bYYP9STp9ehYyg+TGR1eQ JfCP30rpDBXQAnKKkLTNNVluKWl7cl9NVkKjXU0o= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 565D861A87 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=spjoshi@codeaurora.org From: Sarangdhar Joshi To: Andy Gross , David Brown , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stephen Boyd , Trilok Soni , Sarangdhar Joshi Subject: [PATCH 3/4] arm64: dts: msm8996: Add SMEM DT nodes Date: Thu, 20 Oct 2016 11:56:04 -0700 Message-Id: <1476989765-7524-3-git-send-email-spjoshi@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476989765-7524-1-git-send-email-spjoshi@codeaurora.org> References: <1476989765-7524-1-git-send-email-spjoshi@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bjorn Andersson Add SMEM and TCSR DT nodes on MSM8996. Signed-off-by: Bjorn Andersson Signed-off-by: Sarangdhar Joshi --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 949b096..0a810f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -169,12 +169,31 @@ method = "smc"; }; + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + tcsr_mutex_regs: syscon@740000 { + compatible = "syscon"; + reg = <0x740000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + intc: interrupt-controller@9bc0000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;