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[209.132.180.67]) by mx.google.com with ESMTP id h19si28143238pgn.301.2016.10.17.09.32.41; Mon, 17 Oct 2016 09:32:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936166AbcJQQcS (ORCPT + 27 others); Mon, 17 Oct 2016 12:32:18 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:33195 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936073AbcJQQcB (ORCPT ); Mon, 17 Oct 2016 12:32:01 -0400 Received: by mail-pf0-f171.google.com with SMTP id 128so81560772pfz.0 for ; Mon, 17 Oct 2016 09:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q9ZtOwHSDGmflYRMu9ZPbva9tJUAiItqLnujDDU0u8c=; b=DKmjRHPp4NshMSupgu4dAwH9BGzu+zdON8/H2Q593L9GcpbuVbuO7dHDcR0v2vuyCi HmhfQ9XX983VRweQQ2DIEgR9Z4Es+W8oGyU/A+DfWsUqnMIqTfWLRJ1Z1smv8TYGUf5t sxOefi4NIAkPqgJTmdMyUVH40v9TviZfDz3ak= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q9ZtOwHSDGmflYRMu9ZPbva9tJUAiItqLnujDDU0u8c=; b=c3LVaO4Hy2XSoUK+wF15AF4dCngZsDitu39kJVsvQgX+k735Rj/H8VOckssTYYqRZH ho6CxwCfC1fZ8F4QeabJ/Xh2dMp6icziLqMgnA8ptwoOq4eevbsDYYYFwadZOBbnu8/w u88ut0CAo4yoAAZhi00sncC+Kgc2udUaW7ap+d6sn5tZLhNniL2tcdTThQurD+Wl/wDK Fq6qJqjR6LgxsBSQXfyZPYwwXdUa7YUrP+wNvVf0BGNnocZ261PpY6So4ItRf9Kin3Mb 7K8ZVWdoDYsQ68WyJSWzbhOkjPkXNA7GDlGf/yFWqGXqqSyUNE+0qYaUjn2e2O1jCSF1 5bGQ== X-Gm-Message-State: AA6/9RnWch/vYsk7hu5Af9XQO45h0A16P1z+Ifusa2XJze2g3IH+yVMm8jAfnOUccY/XEeVi X-Received: by 10.99.66.130 with SMTP id p124mr32419367pga.30.1476721920091; Mon, 17 Oct 2016 09:32:00 -0700 (PDT) Received: from blr-ubuntu-59.ap.qualcomm.com ([202.46.23.61]) by smtp.gmail.com with ESMTPSA id o9sm43009638pac.27.2016.10.17.09.31.57 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Oct 2016 09:31:59 -0700 (PDT) From: Binoy Jayan To: Doug Ledford , Sean Hefty , Hal Rosenstock Cc: Arnd Bergmann , linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org, Binoy Jayan Subject: [PATCH 8/8] IB/mlx5: Replace counting semaphore sem with wait condition Date: Mon, 17 Oct 2016 22:01:02 +0530 Message-Id: <1476721862-7070-9-git-send-email-binoy.jayan@linaro.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1476721862-7070-1-git-send-email-binoy.jayan@linaro.org> References: <1476721862-7070-1-git-send-email-binoy.jayan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Counting semaphores are going away in the future, so replace the semaphore umr_common::sem with an open-coded implementation. Signed-off-by: Binoy Jayan --- drivers/infiniband/hw/mlx5/main.c | 3 ++- drivers/infiniband/hw/mlx5/mlx5_ib.h | 3 ++- drivers/infiniband/hw/mlx5/mr.c | 28 +++++++++++++++++++--------- 3 files changed, 23 insertions(+), 11 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index 2217477..5667ea8 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2520,7 +2520,8 @@ static int create_umr_res(struct mlx5_ib_dev *dev) dev->umrc.cq = cq; dev->umrc.pd = pd; - sema_init(&dev->umrc.sem, MAX_UMR_WR); + init_waitqueue_head(&dev->umrc.sem.wq); + atomic_set(&dev->umrc.sem.count, MAX_UMR_WR); ret = mlx5_mr_cache_init(dev); if (ret) { mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h index dcdcd19..60e2d29 100644 --- a/drivers/infiniband/hw/mlx5/mlx5_ib.h +++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h @@ -45,6 +45,7 @@ #include #include #include +#include #define mlx5_ib_dbg(dev, format, arg...) \ pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \ @@ -533,7 +534,7 @@ struct umr_common { struct ib_qp *qp; /* control access to UMR QP */ - struct semaphore sem; + struct ib_semaphore sem; }; enum { diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index d4ad672..7c2af26 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -900,7 +900,9 @@ static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, prep_umr_reg_wqe(pd, &umrwr.wr, &sg, dma, npages, mr->mmkey.key, page_shift, virt_addr, len, access_flags); - down(&umrc->sem); + wait_event(umrc->sem.wq, + atomic_add_unless(&umrc->sem.count, -1, 0)); + err = ib_post_send(umrc->qp, &umrwr.wr, &bad); if (err) { mlx5_ib_warn(dev, "post send failed, err %d\n", err); @@ -920,7 +922,8 @@ static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem, mr->live = 1; unmap_dma: - up(&umrc->sem); + if (atomic_inc_return(&umrc->sem.count) == 1) + wake_up(&umrc->sem.wq); dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); kfree(mr_pas); @@ -1031,7 +1034,8 @@ int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, int npages, wr.mkey = mr->mmkey.key; wr.target.offset = start_page_index; - down(&umrc->sem); + wait_event(umrc->sem.wq, + atomic_add_unless(&umrc->sem.count, -1, 0)); err = ib_post_send(umrc->qp, &wr.wr, &bad); if (err) { mlx5_ib_err(dev, "UMR post send failed, err %d\n", err); @@ -1043,7 +1047,8 @@ int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index, int npages, err = -EFAULT; } } - up(&umrc->sem); + if (atomic_inc_return(&umrc->sem.count) == 1) + wake_up(&umrc->sem.wq); } dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); @@ -1224,15 +1229,18 @@ static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr) umrwr.wr.wr_cqe = &umr_context.cqe; prep_umr_unreg_wqe(dev, &umrwr.wr, mr->mmkey.key); - down(&umrc->sem); + wait_event(umrc->sem.wq, + atomic_add_unless(&umrc->sem.count, -1, 0)); err = ib_post_send(umrc->qp, &umrwr.wr, &bad); if (err) { - up(&umrc->sem); + if (atomic_inc_return(&umrc->sem.count) == 1) + wake_up(&umrc->sem.wq); mlx5_ib_dbg(dev, "err %d\n", err); goto error; } else { wait_for_completion(&umr_context.done); - up(&umrc->sem); + if (atomic_inc_return(&umrc->sem.count) == 1) + wake_up(&umrc->sem.wq); } if (umr_context.status != IB_WC_SUCCESS) { mlx5_ib_warn(dev, "unreg umr failed\n"); @@ -1291,7 +1299,8 @@ static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, u64 virt_addr, } /* post send request to UMR QP */ - down(&umrc->sem); + wait_event(umrc->sem.wq, + atomic_add_unless(&umrc->sem.count, -1, 0)); err = ib_post_send(umrc->qp, &umrwr.wr, &bad); if (err) { @@ -1305,7 +1314,8 @@ static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr, u64 virt_addr, } } - up(&umrc->sem); + if (atomic_inc_return(&umrc->sem.count) == 1) + wake_up(&umrc->sem.wq); if (flags & IB_MR_REREG_TRANS) { dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE); kfree(mr_pas);