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[209.132.180.67]) by mx.google.com with ESMTP id 132si25060810pfw.133.2016.09.26.05.33.08; Mon, 26 Sep 2016 05:33:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034751AbcIZMcy (ORCPT + 27 others); Mon, 26 Sep 2016 08:32:54 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:36802 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1034582AbcIZMct (ORCPT ); Mon, 26 Sep 2016 08:32:49 -0400 Received: by mail-pa0-f41.google.com with SMTP id qn7so45277149pac.3 for ; Mon, 26 Sep 2016 05:32:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Sp073HDQbDI3K6X+VWyR2X/rDvt5anoYpDdGVWsitLM=; b=JOUKGPpRBeNZnhDJYRbHpy9Q427eiTZdKhIFH6vNiCIGwP7HYbPeywbz5HRNKrNa7L 2BZB86WUTkij5UN77QGtKTtGUmMyghIUAjVhnSms/fOJH0zdS+oAruth3ZEoxqpVHVqj r0rt+V0cpJ4ksOd1Typ5WjV9WoQvXt9F9Gw9A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Sp073HDQbDI3K6X+VWyR2X/rDvt5anoYpDdGVWsitLM=; b=gR291PQEDkd53hEx/RSh+cyHhYvQT8DV2bCm1RHIEzxKOjKvOwEAwDc9AdXFVzF0NR tcAUikzgpSHj77c5FjKg64pLFtFa3pwV6EJAxkimbnLYfsUBl8jqSw4+IsBtWPENQTVP 6fQRRHCK32aybXlCf6SIk1bw96zogaqFtQW02x8ejDMuKUDLWjF5dX6lcAenE0sktj/P abTZ/twT6qjSsKxIY0nBJHiK+6LcuHUsFDui39ZmuKmizkN6z/MiFY40jLfZoRiYgmh7 Ph2X/O1ZlR4FQVRkosa7H+qGiMxPcjgONbMnUviuzHQ6emwlCTJ0ugLJ1P7wzJDWzZoO Hz/A== X-Gm-Message-State: AE9vXwMBR82gynOsXajo47XOCTL8rRxTwMOkVfflfaq1try1a67NL7xgv29fqxKqfVS4LBbX X-Received: by 10.66.188.202 with SMTP id gc10mr37377454pac.104.1474893168559; Mon, 26 Sep 2016 05:32:48 -0700 (PDT) Received: from localhost.localdomain ([67.238.99.186]) by smtp.gmail.com with ESMTPSA id c15sm10893809pfl.25.2016.09.26.05.32.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Sep 2016 05:32:47 -0700 (PDT) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org, bskeggs@redhat.com, airlied@linux.ie, dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org Cc: Ard Biesheuvel Subject: [PATCH v4 1/3] drm/nouveau: set streaming DMA mask early Date: Mon, 26 Sep 2016 05:32:38 -0700 Message-Id: <1474893160-12321-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474893160-12321-1-git-send-email-ard.biesheuvel@linaro.org> References: <1474893160-12321-1-git-send-email-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some subdevices (i.e., fb/nv50.c and fb/gf100.c) map a scratch page using dma_map_page() way before the TTM layer has had a chance to set the DMA mask. This may prevent the driver from loading at all on platforms whose system memory is not covered by the default DMA mask of 32-bit (i.e., when all RAM is above 4 GB). So set a preliminary DMA mask right after constructing the PCI device, and base it on the .dma_bits member of the MMU subdevice, which is what the TTM layer will base the DMA mask on as well. Signed-off-by: Ard Biesheuvel --- drivers/gpu/drm/nouveau/nouveau_drm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.7.4 diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 652ab111dd74..e61e9a0adb51 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -361,6 +361,17 @@ static int nouveau_drm_probe(struct pci_dev *pdev, pci_set_master(pdev); + /* + * Set a preliminary DMA mask based on the .dma_bits member of the + * MMU subdevice. This allows other subdevices to create DMA mappings + * in their init() function, which are called before the TTM layer sets + * the DMA mask definitively. + * This is necessary for platforms where the default DMA mask of 32 + * does not cover any system memory, i.e., when all RAM is > 4 GB. + */ + dma_set_mask_and_coherent(device->dev, + DMA_BIT_MASK(device->mmu->dma_bits)); + ret = drm_get_pci_dev(pdev, pent, &driver_pci); if (ret) { nvkm_device_del(&device);