From patchwork Tue Sep 13 17:10:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 76099 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp1465566qgf; Tue, 13 Sep 2016 10:14:03 -0700 (PDT) X-Received: by 10.98.18.8 with SMTP id a8mr3107496pfj.57.1473786843852; Tue, 13 Sep 2016 10:14:03 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 191si28402071pfz.229.2016.09.13.10.14.03; Tue, 13 Sep 2016 10:14:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760067AbcIMRN7 (ORCPT + 27 others); Tue, 13 Sep 2016 13:13:59 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:49414 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759799AbcIMRM6 (ORCPT ); Tue, 13 Sep 2016 13:12:58 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8DHBvRL023894; Tue, 13 Sep 2016 12:11:57 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8DHBuB5017038; Tue, 13 Sep 2016 12:11:56 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 13 Sep 2016 12:11:54 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8DHAuWx013681; Tue, 13 Sep 2016 12:11:50 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Arnd Bergmann , Jingoo Han , , , , , Pratyush Anand CC: , , , , , , Joao Pinto , Rob Herring , , Subject: [RFC PATCH] ARM: dts: DRA7: Modify pcie1 dt node for EP mode Date: Tue, 13 Sep 2016 22:40:52 +0530 Message-ID: <1473786653-12759-11-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473786653-12759-1-git-send-email-kishon@ti.com> References: <1473786653-12759-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Modify pcie1 dt node in order for the controller to operate in endpoint mode. This is used only for testing EP mode. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi | 43 +++++++++++-------------------------------- 1 file changed, 11 insertions(+), 32 deletions(-) -- 1.7.9.5 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d9bfb94..73f63d1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -283,38 +283,17 @@ }; }; - axi@0 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; - pcie1: pcie@51000000 { - compatible = "ti,dra7-pcie"; - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - #interrupt-cells = <1>; - num-lanes = <1>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 1>, - <0 0 0 2 &pcie1_intc 2>, - <0 0 0 3 &pcie1_intc 3>, - <0 0 0 4 &pcie1_intc 4>; - pcie1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; + pcie1: pcie@51000000 { + compatible = "ti,dra7-pcie-ep"; + reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>; + reg-names = "ep_dbics", "ti_conf", "ep_dbics2"; + interrupts = <0 232 0x4>; + num-lanes = <1>; + num-ib-windows = <4>; + num-ob-windows = <16>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; }; axi@1 {