From patchwork Tue Aug 16 10:19:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 73988 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp1917228qga; Tue, 16 Aug 2016 03:26:41 -0700 (PDT) X-Received: by 10.66.147.234 with SMTP id tn10mr11643946pab.144.1471343201490; Tue, 16 Aug 2016 03:26:41 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y186si31581579pfb.59.2016.08.16.03.26.39; Tue, 16 Aug 2016 03:26:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753390AbcHPK0h (ORCPT + 27 others); Tue, 16 Aug 2016 06:26:37 -0400 Received: from foss.arm.com ([217.140.101.70]:45997 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752985AbcHPK0f (ORCPT ); Tue, 16 Aug 2016 06:26:35 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 640EF318; Tue, 16 Aug 2016 03:21:06 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5530C3F32C; Tue, 16 Aug 2016 03:19:32 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, Christopher Covington Cc: Sudeep Holla , Thomas Gleixner , Jason Cooper , Marc Zyngier , Lorenzo Pieralisi Subject: [PATCH] irqchip/gicv3: remove disabling redistributor and group1 non-secure interrupts Date: Tue, 16 Aug 2016 11:19:26 +0100 Message-Id: <1471342766-18445-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As per the GICv3 specification, to power down a processor using GICv3 and allow automatic power-on if an interrupt must be sent to a processor, software must set Enable to zero for all interrupt groups(by writing to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate. When commit 3708d52fc6bb ("irqchip: gic-v3: Implement CPU PM notifier") was introduced there were no firmware implementations(in particular PSCI) handling this. Linux kernel may not be aware of the CPU power state details and might fail to identify the power states that require quiescing the CPU interface. Even if it can be aware of those details, it can't determine which CPU power state have been triggered at the platform level and how the power control is implemented. This patch make disabling redistributor and group1 non-secure interrupts in the power down path and re-enabling of redistributor in the power-up path conditional. It will be handled in the kernel if and only if the non-secure accesses are permitted to access and modify control registers. It is left to the platform implementation otherwise. Cc: Marc Zyngier Cc: Lorenzo Pieralisi Signed-off-by: Sudeep Holla --- drivers/irqchip/irq-gic-v3.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) Hi Christopher, Can you check if ACPI processor idle works with this patch on QDF2432 ? PSCI implementation much now deal with Grp1 interrupts when CPU is being powered down during suspend/resume. I have pushed changes to ARM TF[1] Regards, Sudeep [1] https://github.com/sudeep-holla/arm-trusted-firmware/commit/65d68ca64d12a4ce5b05a96808dd6f638451940d -- 2.7.4 diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 6fc56c3466b0..a8db96540ca1 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -119,6 +119,12 @@ static void gic_redist_wait_for_rwp(void) gic_do_wait_for_rwp(gic_data_rdist_rd_base()); } +/* Check whether it's single security state view */ +static bool gic_dist_security_disabled(void) +{ + return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; +} + #ifdef CONFIG_ARM64 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); @@ -671,9 +677,10 @@ static int gic_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) { if (cmd == CPU_PM_EXIT) { - gic_enable_redist(true); + if (gic_dist_security_disabled()) + gic_enable_redist(true); gic_cpu_sys_reg_init(); - } else if (cmd == CPU_PM_ENTER) { + } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { gic_write_grpen1(0); gic_enable_redist(false); }