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[82.33.25.72]) by smtp.gmail.com with ESMTPSA id d64sm2840227wmc.22.2016.08.11.04.55.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Aug 2016 04:55:26 -0700 (PDT) From: Daniel Thompson To: Thomas Gleixner , Jason Cooper , Russell King , Marc Zyngier Cc: Daniel Thompson , Will Deacon , Catalin Marinas , Stephen Boyd , John Stultz , Steven Rostedt , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-kernel@lists.linaro.org, Sumit Semwal , Dirk Behme , Daniel Drake , Dmitry Pervushin , Tim Sander , Petr Mladek , Lucas Stach Subject: [PATCH 4.8-rc1 v23 4/4] ARM: Allow IPI_CPU_BACKTRACE to exploit FIQ Date: Thu, 11 Aug 2016 12:55:15 +0100 Message-Id: <1470916515-28510-5-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470916515-28510-1-git-send-email-daniel.thompson@linaro.org> References: <1436188438-9478-1-git-send-email-daniel.thompson@linaro.org> <1470916515-28510-1-git-send-email-daniel.thompson@linaro.org> The GIC (v1 & v2) driver allows its implementation of handle_arch_irq() to be called from the FIQ handler but currently the ARM code is not able to exploit this. Extend handle_fiq_as_nmi() to call handle_arch_irq(). This will affect all interrupt controllers, including ones that do not support FIQ. This is OK because a spurious FIQ is normally fatal. Handling a spurious FIQ like a normal interrupt does risk deadlock but does give us a chance of surviving long enough to get an error message out. We also extend the SMP code to indicate to irq drivers which IPIs they should seek to implement using FIQ. Signed-off-by: Daniel Thompson --- arch/arm/include/asm/smp.h | 9 +++++++++ arch/arm/kernel/smp.c | 6 ++++++ arch/arm/kernel/traps.c | 11 ++++++++++- 3 files changed, 25 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 3d6dc8b460e4..daf869cff02e 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -18,6 +18,15 @@ # error " included in non-SMP build" #endif +/* + * Identify which IPIs are safe for the irqchip to handle using FIQ. + * + * This information is advisory. The interrupt controller may not be capable + * of routing these IPIs to FIQ and the kernel will continue to work if they + * are routed to IRQ as normal. + */ +#define SMP_IPI_FIQ_MASK 0x80 + #define raw_smp_processor_id() (current_thread_info()->cpu) struct seq_file; diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 861521606c6d..5e955ad80a1e 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -644,6 +644,11 @@ void handle_IPI(int ipinr, struct pt_regs *regs) break; case IPI_CPU_BACKTRACE: + if (in_nmi()) { + nmi_cpu_backtrace(regs); + break; + } + printk_nmi_enter(); irq_enter(); nmi_cpu_backtrace(regs); @@ -757,6 +762,7 @@ static void raise_nmi(cpumask_t *mask) if (cpumask_test_cpu(smp_processor_id(), mask) && irqs_disabled()) nmi_cpu_backtrace(NULL); + BUILD_BUG_ON(SMP_IPI_FIQ_MASK != BIT(IPI_CPU_BACKTRACE)); smp_cross_call(mask, IPI_CPU_BACKTRACE); } diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index bc698383e822..8f6173cd0a54 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -479,7 +479,16 @@ asmlinkage void __exception_irq_entry handle_fiq_as_nmi(struct pt_regs *regs) nmi_enter(); - /* nop. FIQ handlers for special arch/arm features can be added here. */ + /* + * Either the interrupt controller supports FIQ, meaning it will + * do the right thing with this call, or we will end up treating a + * spurious FIQ (which is normally fatal) as though it were an IRQ + * which, although it risks deadlock, still gives us a sporting + * chance of surviving long enough to log errors. + */ +#ifdef CONFIG_MULTI_IRQ_HANDLER + handle_arch_irq(regs); +#endif nmi_exit();