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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=prL2jCKniz4sJgAopv60L11lNX4aqn8RlQERFOQgvbA=; b=oPXeh1uFKbV3NZlbljxxyeteNC+5IUV2NGSALEFunmhOs2b26F2FTlxlCxYM0m8BkG0K8mKrBNuUpKJeUGbbHioGIMYf52qNRKoD8x37uyviC3FCv5zIRRowcVe3iVEd0A35B7gMCBCjNfvgIcX98skZuV9wV0HVGfkztWrm7Os= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (114.109.128.54) by BLUPR12MB0434.namprd12.prod.outlook.com (10.162.92.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.549.15; Mon, 25 Jul 2016 09:32:37 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit , Suravee Suthikulpanit Subject: [PART2 PATCH v5 02/12] iommu/amd: Move and introduce new IRTE-related unions and structures Date: Mon, 25 Jul 2016 04:32:01 -0500 Message-ID: <1469439131-11308-3-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469439131-11308-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1469439131-11308-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [114.109.128.54] X-ClientProxiedBy: SG2PR06CA0066.apcprd06.prod.outlook.com (10.167.73.162) To BLUPR12MB0434.namprd12.prod.outlook.com (10.162.92.14) X-MS-Office365-Filtering-Correlation-Id: 71a7e4bb-f255-4fc9-4b04-08d3b46ea2ac X-Microsoft-Exchange-Diagnostics: 1; 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This is mainly to simplify variable declarations in subsequent patches. Besides, this patch also introduces new struct irte_ga for the new 128-bit IRTE format. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 28 --------------- drivers/iommu/amd_iommu_types.h | 78 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 28 deletions(-) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 634f636..ac2962f 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -3693,34 +3693,6 @@ EXPORT_SYMBOL(amd_iommu_device_info); * *****************************************************************************/ -union irte { - u32 val; - struct { - u32 valid : 1, - no_fault : 1, - int_type : 3, - rq_eoi : 1, - dm : 1, - rsvd_1 : 1, - destination : 8, - vector : 8, - rsvd_2 : 8; - } fields; -}; - -struct irq_2_irte { - u16 devid; /* Device ID for IRTE table */ - u16 index; /* Index into IRTE table*/ -}; - -struct amd_ir_data { - struct irq_2_irte irq_2_irte; - union irte irte_entry; - union { - struct msi_msg msi_entry; - }; -}; - static struct irq_chip amd_ir_chip; #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 25f939b..d9227a9 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -706,4 +707,81 @@ enum amd_iommu_intr_mode_type { x == AMD_IOMMU_GUEST_IR_LEGACY_GA) #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) + +union irte { + u32 val; + struct { + u32 valid : 1, + no_fault : 1, + int_type : 3, + rq_eoi : 1, + dm : 1, + rsvd_1 : 1, + destination : 8, + vector : 8, + rsvd_2 : 8; + } fields; +}; + +union irte_ga_lo { + u64 val; + + /* For int remapping */ + struct { + u64 valid : 1, + no_fault : 1, + /* ------ */ + int_type : 3, + rq_eoi : 1, + dm : 1, + /* ------ */ + guest_mode : 1, + destination : 8, + rsvd : 48; + } fields_remap; + + /* For guest vAPIC */ + struct { + u64 valid : 1, + no_fault : 1, + /* ------ */ + ga_log_intr : 1, + rsvd1 : 3, + is_run : 1, + /* ------ */ + guest_mode : 1, + destination : 8, + rsvd2 : 16, + ga_tag : 32; + } fields_vapic; +}; + +union irte_ga_hi { + u64 val; + struct { + u64 vector : 8, + rsvd_1 : 4, + ga_root_ptr : 40, + rsvd_2 : 12; + } fields; +}; + +struct irte_ga { + union irte_ga_lo lo; + union irte_ga_hi hi; +}; + +struct irq_2_irte { + u16 devid; /* Device ID for IRTE table */ + u16 index; /* Index into IRTE table*/ +}; + +struct amd_ir_data { + struct irq_2_irte irq_2_irte; + union irte irte_entry; + union { + struct msi_msg msi_entry; + }; +}; + #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */