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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=bsegDKANfQ+A7S/S8MMNHYYr+iF+xr/45BIfF/4fwiE=; b=fS1NOgO6xuXxnx0t/ztarGKtX0V0Yedf4Ltsj4mcgeiikgP0bE/7I719PCY9U4+CLalZF6+hLb3Aa8TWbLXFXah/2+Y+o8Jw14nINfYZYUv18rNRAk8Uxv1gKrv6FJ0e7SEISu3eoxpPPoMQgWRR84CohABFhK6NXR0G4WQ7oMI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (124.121.8.20) by CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) with Microsoft SMTP Server (TLS) id 15.1.534.14; Mon, 11 Jul 2016 10:12:42 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit Subject: [PART2 PATCH v3 07/11] iommu/amd: Introduce amd_iommu_update_ga() Date: Mon, 11 Jul 2016 05:11:35 -0500 Message-ID: <1468231899-6987-8-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: SG2PR03CA0026.apcprd03.prod.outlook.com (10.160.233.36) To CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) X-MS-Office365-Filtering-Correlation-Id: 00fa178e-22d6-45db-f3de-08d3a973e72d X-Microsoft-Exchange-Diagnostics: 1; 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Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 63 +++++++++++++++++++++++++++++++++++++++++ drivers/iommu/amd_iommu_types.h | 1 + include/linux/amd-iommu.h | 9 ++++++ 3 files changed, 73 insertions(+) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 939ebb8..95f106a 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -4481,4 +4481,67 @@ int amd_iommu_create_irq_domain(struct amd_iommu *iommu) return 0; } + +static int +update_irte_ga(struct irte_ga *irte, unsigned int devid, + u64 base, int cpu, bool is_run) +{ + struct irq_remap_table *irt = get_irq_table(devid, false); + unsigned long flags; + + if (!irt) + return -ENODEV; + + spin_lock_irqsave(&irt->lock, flags); + + if (irte->lo.fields_vapic.guest_mode) { + irte->hi.fields.ga_root_ptr = (base >> 12); + if (cpu >= 0) + irte->lo.fields_vapic.destination = cpu; + irte->lo.fields_vapic.is_run = is_run; + barrier(); + } + + spin_unlock_irqrestore(&irt->lock, flags); + + return 0; +} + +int amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 ga_tag, + u64 base, bool is_run) +{ + unsigned long flags; + struct amd_iommu *iommu; + + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + return 0; + + for_each_iommu(iommu) { + struct amd_ir_data *ir_data; + + spin_lock_irqsave(&iommu->ga_hash_lock, flags); + + /* Note: Update all possible ir_data for a particular + * vcpu in a particular vm. + */ + hash_for_each_possible(iommu->ga_hash, ir_data, hnode, + AMD_IOMMU_GATAG(ga_tag, vcpu_id)) { + struct irte_ga *irte = (struct irte_ga *) ir_data->entry; + + if (!irte->lo.fields_vapic.guest_mode) + continue; + + update_irte_ga((struct irte_ga *)ir_data->ref, + ir_data->irq_2_irte.devid, + base, cpu, is_run); + iommu_flush_irt(iommu, ir_data->irq_2_irte.devid); + iommu_completion_wait(iommu); + } + + spin_unlock_irqrestore(&iommu->ga_hash_lock, flags); + } + + return 0; +} +EXPORT_SYMBOL(amd_iommu_update_ga); #endif diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 926ef6e..81c5def 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -838,6 +838,7 @@ struct amd_ir_data { union { struct msi_msg msi_entry; }; + void *ref; /* Pointer to the actual irte */ }; #ifdef CONFIG_IRQ_REMAP diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 8f7a469..9897da8 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -179,6 +179,9 @@ static inline int amd_iommu_detect(void) { return -ENODEV; } /* IOMMU AVIC Function */ extern int amd_iommu_register_ga_log_notifier(int (*notifier)(int, int, int)); +extern int +amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 ga_tag, u64 base, bool is_run); + #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ static inline int @@ -187,6 +190,12 @@ amd_iommu_register_ga_log_notifier(int (*notifier)(int, int, int)) return 0; } +static inline int +amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 ga_tag, u64 base, bool is_run) +{ + return 0; +} + #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ #endif /* _ASM_X86_AMD_IOMMU_H */