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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=kQvMzkWA/4dL3s7v4AZhDW8va7TZUQ48YWVVeLuEy2k=; b=CFeq/XDByNBmHDXzyR4cFc6gNy9/fzcf3xRH782SJvhQFpYaUytsG7WEwkpg8L7vHMGt3FawCoDngTTMXtw9PKWIOdnMe+h0TUIWNbASJGCQzvPz+ZlLSlm/8jyJNYNtXEQfVamGL2VUP4sx+5uR4LdQQXL9BSuJr0g+ndG9LGo= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from localhost.localdomain (124.121.8.20) by CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) with Microsoft SMTP Server (TLS) id 15.1.534.14; Mon, 11 Jul 2016 10:12:49 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit , Suravee Suthikulpanit Subject: [PART2 PATCH v3 09/11] iommu/amd: Enable vAPIC interrupt remapping mode by default Date: Mon, 11 Jul 2016 05:11:37 -0500 Message-ID: <1468231899-6987-10-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1468231899-6987-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: SG2PR03CA0026.apcprd03.prod.outlook.com (10.160.233.36) To CY1PR12MB0444.namprd12.prod.outlook.com (10.163.91.22) X-MS-Office365-Filtering-Correlation-Id: 5e384095-aa4b-44b8-527e-08d3a973ee1c X-Microsoft-Exchange-Diagnostics: 1; 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Currently, it is enabled for all pass-through device if vAPIC mode is enabled. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 44 +++++++++++++++++++++++++++++++++-------- drivers/iommu/amd_iommu_init.c | 12 ++++++++++- drivers/iommu/amd_iommu_types.h | 2 +- 3 files changed, 48 insertions(+), 10 deletions(-) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index 4abced5..a0afc7d 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -105,6 +105,7 @@ struct iommu_dev_data { bool pri_tlp; /* PASID TLB required for PPR completions */ u32 errata; /* Bitmap for errata to apply */ + u32 use_vapic; /* Enable device to use vapic mode */ }; /* @@ -3238,6 +3239,12 @@ static void amd_iommu_detach_device(struct iommu_domain *dom, if (!iommu) return; +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + (dom->type == IOMMU_DOMAIN_UNMANAGED)) + dev_data->use_vapic = 0; +#endif + iommu_completion_wait(iommu); } @@ -3263,6 +3270,15 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, ret = attach_device(dev, domain); +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { + if (dom->type == IOMMU_DOMAIN_UNMANAGED) + dev_data->use_vapic = 1; + else + dev_data->use_vapic = 0; + } +#endif + iommu_completion_wait(iommu); return ret; @@ -4013,7 +4029,7 @@ static void free_irte(u16 devid, int index) static void irte_prepare(void *entry, u32 delivery_mode, u32 dest_mode, - u8 vector, u32 dest_apicid) + u8 vector, u32 dest_apicid, int devid) { union irte *irte = (union irte *) entry; @@ -4027,13 +4043,14 @@ static void irte_prepare(void *entry, static void irte_ga_prepare(void *entry, u32 delivery_mode, u32 dest_mode, - u8 vector, u32 dest_apicid) + u8 vector, u32 dest_apicid, int devid) { struct irte_ga *irte = (struct irte_ga *) entry; + struct iommu_dev_data *dev_data = search_dev_data(devid); irte->lo.val = 0; irte->hi.val = 0; - irte->lo.fields_remap.guest_mode = 0; + irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0; irte->lo.fields_remap.int_type = delivery_mode; irte->lo.fields_remap.dm = dest_mode; irte->hi.fields.vector = vector; @@ -4087,11 +4104,14 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, u8 vector, u32 dest_apicid) { struct irte_ga *irte = (struct irte_ga *) entry; + struct iommu_dev_data *dev_data = search_dev_data(devid); - irte->hi.fields.vector = vector; - irte->lo.fields_remap.destination = dest_apicid; - irte->lo.fields_remap.guest_mode = 0; - modify_irte_ga(devid, index, irte, NULL); + if (!dev_data || !dev_data->use_vapic) { + irte->hi.fields.vector = vector; + irte->lo.fields_remap.destination = dest_apicid; + irte->lo.fields_remap.guest_mode = 0; + modify_irte_ga(devid, index, irte, NULL); + } } #define IRTE_ALLOCATED (~1U) @@ -4234,7 +4254,7 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data, data->irq_2_irte.index = index + sub_handle; iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, apic->irq_dest_mode, irq_cfg->vector, - irq_cfg->dest_apicid); + irq_cfg->dest_apicid, devid); switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: @@ -4435,6 +4455,14 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) struct amd_ir_data *ir_data = data->chip_data; struct irte_ga *irte = (struct irte_ga *) ir_data->entry; struct irq_2_irte *irte_info = &ir_data->irq_2_irte; + struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); + + /* Note: + * This device has never been set up for guest mode. + * we should not modify the IRTE + */ + if (!dev_data || !dev_data->use_vapic) + return 0; /* Note: * SVM tries to set up for VAPIC mode, but we are in diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index d103c3f..f4722a0 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -146,7 +146,7 @@ struct ivmd_header { bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; -int amd_iommu_guest_ir; +int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static bool amd_iommu_detected; static bool __initdata amd_iommu_disabled; @@ -2014,6 +2014,11 @@ static void early_enable_iommus(void) iommu_enable(iommu); iommu_flush_all_caches(iommu); } + +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); +#endif } static void enable_iommus_v2(void) @@ -2039,6 +2044,11 @@ static void disable_iommus(void) for_each_iommu(iommu) iommu_disable(iommu); + +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); +#endif } /* diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 81c5def..97b706d 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -821,7 +821,7 @@ struct irq_2_irte { }; struct amd_irte_ops { - void (*prepare)(void *, u32, u32, u8, u32); + void (*prepare)(void *, u32, u32, u8, u32, int); void (*activate)(void *, u16, u16); void (*deactivate)(void *, u16, u16); void (*set_affinity)(void *, u16, u16, u8, u32);