From patchwork Fri Jun 24 08:28:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 70801 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp830431qgy; Fri, 24 Jun 2016 01:32:12 -0700 (PDT) X-Received: by 10.66.235.163 with SMTP id un3mr5379165pac.93.1466757132234; Fri, 24 Jun 2016 01:32:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d185si5548873pfa.76.2016.06.24.01.32.11; Fri, 24 Jun 2016 01:32:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751295AbcFXI2m (ORCPT + 30 others); Fri, 24 Jun 2016 04:28:42 -0400 Received: from arroyo.ext.ti.com ([198.47.19.12]:54914 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751084AbcFXI2i (ORCPT ); Fri, 24 Jun 2016 04:28:38 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u5O8SXbB019205; Fri, 24 Jun 2016 03:28:33 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5O8SWnB028855; Fri, 24 Jun 2016 03:28:32 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Fri, 24 Jun 2016 03:28:32 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5O8SMhF018308; Fri, 24 Jun 2016 03:28:29 -0500 From: Keerthy To: , , CC: , , , , , Dave Gerlach Subject: [PATCH v2 3/5] regulator: tps65218: force set power-up/down strobe to 3 for dcdc3 Date: Fri, 24 Jun 2016 13:58:09 +0530 Message-ID: <1466756892-17015-3-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466756892-17015-1-git-send-email-j-keerthy@ti.com> References: <1466756892-17015-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tero Kristo The reset value for this register seems broken on certain versions of tps65218 chip, so make sure the dcdc3 settings is proper. Needed for proper functionality of rtc+ddr / rtc-only modes. Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Keerthy --- drivers/regulator/tps65218-regulator.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/drivers/regulator/tps65218-regulator.c b/drivers/regulator/tps65218-regulator.c index 8eca1eb..d1e631d 100644 --- a/drivers/regulator/tps65218-regulator.c +++ b/drivers/regulator/tps65218-regulator.c @@ -180,8 +180,12 @@ static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev) if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1) return -EINVAL; - if (!tps->info[rid]->strobe) - return -EINVAL; + if (!tps->info[rid]->strobe) { + if (rid == TPS65218_DCDC_3) + tps->info[rid]->strobe = 3; + else + return -EINVAL; + } return tps65218_set_bits(tps, dev->desc->bypass_reg, dev->desc->bypass_mask,