From patchwork Wed Jun 22 10:15:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 70621 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp2468583qgy; Wed, 22 Jun 2016 03:15:50 -0700 (PDT) X-Received: by 10.66.197.202 with SMTP id iw10mr34264510pac.148.1466590550552; Wed, 22 Jun 2016 03:15:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id zk17si11555987pab.0.2016.06.22.03.15.50; Wed, 22 Jun 2016 03:15:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752197AbcFVKPs (ORCPT + 30 others); Wed, 22 Jun 2016 06:15:48 -0400 Received: from foss.arm.com ([217.140.101.70]:46421 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751601AbcFVKPn (ORCPT ); Wed, 22 Jun 2016 06:15:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DEDDC226; Wed, 22 Jun 2016 03:16:10 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.207.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 110F23F213; Wed, 22 Jun 2016 03:15:22 -0700 (PDT) From: Sudeep Holla To: Mathieu Poirier Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki Poulose Subject: [PATCH] coresight: etm4x: request to retain power to the trace unit when active Date: Wed, 22 Jun 2016 11:15:13 +0100 Message-Id: <1466590513-22505-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Coresight ETMv4 architecture provides a way to request to keep the power to the trace unit. This might help to collect the traces without the need to disable the CPU power management(entering/exiting deeper idle states). Trace PowerDown Control Register provides powerup request bit which when set requests the system to retain power to the trace unit and emulate the powerdown request. Typically, a trace unit drives a signal to the power controller to request that the trace unit core power domain is powered up. However, if the trace unit and the CPU are in the same power domain then the implementation might combine the trace unit power up status with a signal from the CPU. This patch requests to retain power to the trace unit when active and to remove when inactive. Note this change will only request but the behaviour depends on the implementation. However, it matches the exact behaviour expected when the external debugger is connected with respect to CPU power states. Cc: Mathieu Poirier Signed-off-by: Sudeep Holla --- drivers/hwtracing/coresight/coresight-etm4x.c | 9 +++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 2 files changed, 12 insertions(+) Hi Mathieu, This is tested on Juno, and on Juno the trace unit core power domain and CPU power domain are shared. So we can manage just with the trace unit debug power domain info from the DT as done with my Juno DT patch series. Regards, Sudeep -- 2.7.4 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d6f1d6d874eb..301ee3232f3d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -163,6 +163,12 @@ static void etm4_enable_hw(void *info) writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); + /* + * Request to keep the trace unit powered and also + * emulation of powerdown + */ + writel_relaxed(TRCPDCR_PU, drvdata->base + TRCPDCR); + /* Enable the trace unit */ writel_relaxed(1, drvdata->base + TRCPRGCTLR); @@ -293,6 +299,9 @@ static void etm4_disable_hw(void *info) CS_UNLOCK(drvdata->base); + /* power can be removed from the trace unit now */ + writel_relaxed(0, drvdata->base + TRCPDCR); + control = readl_relaxed(drvdata->base + TRCPRGCTLR); /* EN, bit[0] Trace unit enable bit */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 5359c5197c1d..2629954429a1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -183,6 +183,9 @@ #define TRCSTATR_IDLE_BIT 0 #define ETM_DEFAULT_ADDR_COMP 0 +/* PowerDown Control Register bits */ +#define TRCPDCR_PU BIT(3) + /* secure state access levels */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9)