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c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=PMUstY808rypbMc4Bp9f3HD+S9aTVA9dI7DXh9b59U4=; b=J5jdaXwV9kIt2pSRY0bjWStOrk/gXUs7SWjBLRPnRBhlTiI1ivIPKOduUGu3/zsGBUOvT/ZcEADhX+uyj+WzuDa6cMt7Rxv02Q6WwUr5OTBsvHXmiMwyyKGrdT5TDzjLMBFBmJxzyn2e41TfJDF9SY6fY0GKhxlxfIfxDyYDE+k= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; Received: from ssuthiku-cz-dev.amd.com (165.204.77.1) by BLUPR12MB0434.namprd12.prod.outlook.com (10.162.92.14) with Microsoft SMTP Server (TLS) id 15.1.517.8; Mon, 13 Jun 2016 22:07:05 +0000 From: Suravee Suthikulpanit To: , , , CC: , , , Suravee Suthikulpanit Subject: [PART2 RFC v2 06/10] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices Date: Mon, 13 Jun 2016 17:06:46 -0500 Message-ID: <1465855611-10092-7-git-send-email-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465855611-10092-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1465855611-10092-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN1PR0701CA0005.namprd07.prod.outlook.com (10.162.96.15) To BLUPR12MB0434.namprd12.prod.outlook.com (10.162.92.14) X-MS-Office365-Filtering-Correlation-Id: 247b7e48-b296-4c6b-a091-08d393d70e3c X-Microsoft-Exchange-Diagnostics: 1; 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In case requirements for vapic mode are not met, it falls back to set up the IRTE in legacy mode. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd_iommu.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/amd-iommu.h | 6 +++++ 2 files changed, 71 insertions(+) -- 1.9.1 diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index d6a56ac..7176c94 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -4334,6 +4334,70 @@ static struct irq_domain_ops amd_ir_domain_ops = { .deactivate = irq_remapping_deactivate, }; +static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) +{ + unsigned long flags; + struct amd_iommu *iommu; + struct amd_iommu_pi_data *pi_data = vcpu_info; + struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; + struct amd_ir_data *ir_data = data->chip_data; + struct irte_ga *irte = &ir_data->irte_ga_entry; + struct irq_2_irte *irte_info = &ir_data->irq_2_irte; + struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); + + /* Note: + * This device has never been set up for guest mode. + * we should not modify the IRTE + */ + if (!dev_data || !dev_data->use_vapic) + return 0; + + /* Note: + * SVM tries to set up for GA mode, but we are in + * legacy mode. So, we force legacy mode instead. + */ + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { + pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", + __func__); + vcpu_pi_info = NULL; + } + + iommu = amd_iommu_rlookup_table[irte_info->devid]; + if (iommu == NULL) + return -EINVAL; + + spin_lock_irqsave(&iommu->ga_hash_lock, flags); + + if (vcpu_pi_info) { + /* Setting */ + irte->hi.fields.vector = vcpu_pi_info->vector; + irte->lo.fields_vapic.guest_mode = 1; + irte->lo.fields_vapic.ga_tag = + AMD_IOMMU_GATAG(pi_data->avic_tag, pi_data->vcpu_id); + + if (!hash_hashed(&ir_data->hnode)) + hash_add(iommu->ga_hash, &ir_data->hnode, + (u16)(irte->lo.fields_vapic.ga_tag)); + } else { + /* Un-Setting */ + struct irq_cfg *cfg = irqd_cfg(data); + + irte->hi.val = 0; + irte->lo.val = 0; + irte->hi.fields.vector = cfg->vector; + irte->lo.fields_remap.guest_mode = 0; + irte->lo.fields_remap.destination = cfg->dest_apicid; + irte->lo.fields_remap.int_type = apic->irq_delivery_mode; + irte->lo.fields_remap.dm = apic->irq_dest_mode; + + hash_del(&ir_data->hnode); + } + + spin_unlock_irqrestore(&iommu->ga_hash_lock, flags); + + return modify_irte_ga(irte_info->devid, irte_info->index, irte); +} + static int amd_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) { @@ -4385,6 +4449,7 @@ static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) static struct irq_chip amd_ir_chip = { .irq_ack = ir_ack_apic_edge, .irq_set_affinity = amd_ir_set_affinity, + .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, .irq_compose_msi_msg = ir_compose_msi_msg, }; diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index e52cee5..f698900 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -22,6 +22,12 @@ #include +struct amd_iommu_pi_data { + u32 vcpu_id; + u32 avic_tag; + struct vcpu_data *vcpu_data; +}; + #ifdef CONFIG_AMD_IOMMU struct task_struct;