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[209.132.180.67]) by mx.google.com with ESMTP id z62si11876158pfb.179.2016.06.11.21.21.03; Sat, 11 Jun 2016 21:21:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751117AbcFLEVB (ORCPT + 30 others); Sun, 12 Jun 2016 00:21:01 -0400 Received: from 50-232-66-2-static.hfc.comcastbusiness.net ([50.232.66.2]:49899 "EHLO camailhost1.caveonetworks.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750708AbcFLEVA (ORCPT ); Sun, 12 Jun 2016 00:21:00 -0400 X-Greylist: delayed 1273 seconds by postgrey-1.27 at vger.kernel.org; Sun, 12 Jun 2016 00:21:00 EDT Received: from localhost (arm64.caveonetworks.com [10.18.106.16] (may be forged)) by camailhost1.caveonetworks.com (8.14.4/8.13.8) with ESMTP id u5C3wRI0001592; Sat, 11 Jun 2016 20:58:27 -0700 Received: from arm64.caveonetworks.com (localhost [127.0.0.1]) by localhost (8.14.4/8.14.4/Debian-4.1ubuntu1) with ESMTP id u5C3wRNH013277; Sat, 11 Jun 2016 20:58:27 -0700 Received: (from apinski@localhost) by arm64.caveonetworks.com (8.14.4/8.14.4/Submit) id u5C3wQbH013276; Sat, 11 Jun 2016 20:58:26 -0700 From: Andrew Pinski To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pinskia@gmail.com, apinski@cavium.com Subject: [PATCH] perf annotate: ARM64 support Date: Sat, 11 Jun 2016 20:58:22 -0700 Message-Id: <1465703902-13237-1-git-send-email-apinski@cavium.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic support to parse ARM64 assembly. This: * enables perf to correctly show the disassembly, rather than chopping some constants off at the '#'. '#' is not the comment character for ARM64. * allows perf to identify ARM64 instructions that branch to other parts within the same function, thereby properly annotating them. * allows perf to identify function calls, allowing called functions to be followed in the annotated view. Signed-off-by: Andrew Pinski --- tools/perf/util/annotate.c | 64 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 3 deletions(-) -- 1.9.1 diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 7e5a1e8..ea915e8 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -65,7 +65,7 @@ static int call__parse(struct ins_operands *ops) name++; -#ifdef __arm__ +#if defined(__arm__) || defined(__aarch64__) if (strchr(name, '+')) return -1; #endif @@ -119,9 +119,22 @@ bool ins__is_call(const struct ins *ins) static int jump__parse(struct ins_operands *ops) { - const char *s = strchr(ops->raw, '+'); + const char *raw = ops->raw; + const char *s; +#ifdef __aarch64__ + /* Skip over one or two commas so that cbz and tbz works. */ + const char *comma = strchr(raw, ','); + + if (comma) { + raw = comma + 1; + comma = strchr(raw, ','); + if (comma) + raw = comma + 1; + } +#endif + s = strchr(raw, '+'); - ops->target.addr = strtoull(ops->raw, NULL, 16); + ops->target.addr = strtoull(raw, NULL, 16); if (s++ != NULL) ops->target.offset = strtoull(s, NULL, 16); @@ -134,6 +147,25 @@ static int jump__parse(struct ins_operands *ops) static int jump__scnprintf(struct ins *ins, char *bf, size_t size, struct ins_operands *ops) { +#ifdef __aarch64__ + const char *comma0 = strchr(ops->raw, ','); + + if (comma0) { + const char *comma1 = strchr(comma0 + 1, ','); + + if (comma1) + return scnprintf(bf, size, + "%-6.6s %.*s, %.*s, %" PRIx64, + ins->name, + (int)(comma0 - ops->raw), ops->raw, + (int)(comma1 - comma0 - 1), comma0 + 1, + ops->target.offset); + + return scnprintf(bf, size, "%-6.6s %.*s, %" PRIx64, ins->name, + (int)(comma0 - ops->raw), ops->raw, + ops->target.offset); + } +#endif return scnprintf(bf, size, "%-6.6s %" PRIx64, ins->name, ops->target.offset); } @@ -253,6 +285,8 @@ static int mov__parse(struct ins_operands *ops) target = ++s; #ifdef __arm__ comment = strchr(s, ';'); +#elif defined(__aarch64__) + comment = strstr(s, "//"); #else comment = strchr(s, '#'); #endif @@ -355,6 +389,29 @@ static struct ins_ops nop_ops = { }; static struct ins instructions[] = { +#ifdef __aarch64__ + { .name = "b", .ops = &jump_ops, }, // might also be a call + { .name = "b.cc", .ops = &jump_ops, }, + { .name = "b.cs", .ops = &jump_ops, }, + { .name = "b.eq", .ops = &jump_ops, }, + { .name = "b.ge", .ops = &jump_ops, }, + { .name = "b.gt", .ops = &jump_ops, }, + { .name = "b.hi", .ops = &jump_ops, }, + { .name = "b.le", .ops = &jump_ops, }, + { .name = "b.ls", .ops = &jump_ops, }, + { .name = "b.lt", .ops = &jump_ops, }, + { .name = "b.ne", .ops = &jump_ops, }, + { .name = "b.pl", .ops = &jump_ops, }, + { .name = "bl", .ops = &call_ops, }, + { .name = "cbnz", .ops = &jump_ops, }, + { .name = "cbz", .ops = &jump_ops, }, + { .name = "dec", .ops = &dec_ops, }, + { .name = "lock", .ops = &lock_ops, }, // fake one + { .name = "mov", .ops = &mov_ops, }, + { .name = "nop", .ops = &nop_ops, }, + { .name = "tbnz", .ops = &jump_ops, }, + { .name = "tbz", .ops = &jump_ops, }, +#else { .name = "add", .ops = &mov_ops, }, { .name = "addl", .ops = &mov_ops, }, { .name = "addq", .ops = &mov_ops, }, @@ -444,6 +501,7 @@ static struct ins instructions[] = { { .name = "xadd", .ops = &mov_ops, }, { .name = "xbeginl", .ops = &jump_ops, }, { .name = "xbeginq", .ops = &jump_ops, }, +#endif }; static int ins__key_cmp(const void *name, const void *insp)