From patchwork Tue Jun 7 13:59:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 69515 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp1993637qgf; Tue, 7 Jun 2016 07:00:25 -0700 (PDT) X-Received: by 10.98.6.69 with SMTP id 66mr31845551pfg.115.1465308022187; Tue, 07 Jun 2016 07:00:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g132si6167888pfc.38.2016.06.07.07.00.21; Tue, 07 Jun 2016 07:00:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755424AbcFGN77 (ORCPT + 31 others); Tue, 7 Jun 2016 09:59:59 -0400 Received: from mail-lf0-f51.google.com ([209.85.215.51]:33106 "EHLO mail-lf0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755018AbcFGN7z (ORCPT ); Tue, 7 Jun 2016 09:59:55 -0400 Received: by mail-lf0-f51.google.com with SMTP id s64so115858488lfe.0 for ; Tue, 07 Jun 2016 06:59:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PCQljBY2alWpR1NxKtjXs6xxvGkbEGwczkrxXN1muIs=; b=LNq5hGNppsvHOk1q73eaX5iP3/mwtOVeavfko4RGV2cfTFPqDI4bWTnk8msQJFz+6N FagYiHMUOFZ7mEm2qZ5PRq5KLERKcYdMVK1T8nRBS4dFVx0NNpM2DM+fqMMUq2I1z/UO +Wbqhv1BuhjGPoajjyfzIbYR3RcY2GzcYrWew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PCQljBY2alWpR1NxKtjXs6xxvGkbEGwczkrxXN1muIs=; b=aDWyE1OnXFiWZ2QgnrW8x2Ce2idMpzXLrol+Zz3Bx/CjnxQZO+j33eiMaDsdkOnip1 BG5TfvdjO3CGQuDtdzxYoEN92rKOMdszAqh32G5IlqIAjQJ5e/foaAR1rnnQLIkrAgT8 8c05xzGl41NvvRdTBTB3uY8it9+u8JNSZF0o20e3fMykEWuXLXXQmtwZvz1vIAL4s8li XISTaiF0bmo0zsHjz8mrj/BdWTnqTHoN0ajf+2pJshKrx3snI7zBzEPHyjrqzsV9O8u5 vMtjpR1NYFraC03SN4fH/yaWavZ0lkaNfaxOS/xGqdM0BAWUGe4A9QBEj16S/AVSKH/d n1uA== X-Gm-Message-State: ALyK8tJlD1CjY3MHRUu4ZpCih9bWr4RCuyD1g/+9gTwV/dzsJ3JE+lUz5i90DEHitzHLF8vc X-Received: by 10.46.71.20 with SMTP id u20mr1782224lja.18.1465307988546; Tue, 07 Jun 2016 06:59:48 -0700 (PDT) Received: from khorivan.synapse.com ([212.90.63.58]) by smtp.gmail.com with ESMTPSA id g70sm2274758ljg.43.2016.06.07.06.59.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Jun 2016 06:59:47 -0700 (PDT) From: Ivan Khoronzhuk To: mugunthanvnm@ti.com, linux-kernel@vger.kernel.org Cc: grygorii.strashko@ti.com, linux-omap@vger.kernel.org, netdev@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, bcousson@baylibre.com, tony@atomide.com, devicetree@vger.kernel.org, Ivan Khoronzhuk Subject: [PATCH v2 1/2] net: ethernet: ti: cpsw: remove rx_descs property Date: Tue, 7 Jun 2016 16:59:35 +0300 Message-Id: <1465307976-12235-2-git-send-email-ivan.khoronzhuk@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465307976-12235-1-git-send-email-ivan.khoronzhuk@linaro.org> References: <1465307976-12235-1-git-send-email-ivan.khoronzhuk@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is no reason in rx_descs property because davinici_cpdma driver splits pool of descriptors equally between tx and rx channels. That is, if number of descriptors 256, 128 of them are for rx channels. While receiving, the descriptor is freed to the pool and then allocated with new skb. And if in DT the "rx_descs" is set to 64, then 128 - 64 = 64 descriptors are always in the pool and cannot be used, for tx, for instance. It's not correct resource usage, better to set it to half of pool, then the rx pool can be used in full. It will not have any impact on performance, as anyway, the "redundant" descriptors were unused. Signed-off-by: Ivan Khoronzhuk --- drivers/net/ethernet/ti/cpsw.c | 13 +++---------- drivers/net/ethernet/ti/cpsw.h | 1 - drivers/net/ethernet/ti/davinci_cpdma.c | 6 ++++++ drivers/net/ethernet/ti/davinci_cpdma.h | 1 + 4 files changed, 10 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 4b08a2f..db2bdd7 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1277,6 +1277,7 @@ static int cpsw_ndo_open(struct net_device *ndev) ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); if (!cpsw_common_res_usage_state(priv)) { + int buf_num; struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0); /* setup tx dma to fixed prio and zero offset */ @@ -1305,10 +1306,8 @@ static int cpsw_ndo_open(struct net_device *ndev) enable_irq(priv->irqs_table[0]); } - if (WARN_ON(!priv->data.rx_descs)) - priv->data.rx_descs = 128; - - for (i = 0; i < priv->data.rx_descs; i++) { + buf_num = cpdma_chan_get_rx_buf_num(priv->dma); + for (i = 0; i < buf_num; i++) { struct sk_buff *skb; ret = -ENOMEM; @@ -1999,12 +1998,6 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, } data->bd_ram_size = prop; - if (of_property_read_u32(node, "rx_descs", &prop)) { - dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n"); - return -EINVAL; - } - data->rx_descs = prop; - if (of_property_read_u32(node, "mac_control", &prop)) { dev_err(&pdev->dev, "Missing mac_control property in the DT.\n"); return -EINVAL; diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h index e50afd1..16b54c6 100644 --- a/drivers/net/ethernet/ti/cpsw.h +++ b/drivers/net/ethernet/ti/cpsw.h @@ -35,7 +35,6 @@ struct cpsw_platform_data { u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */ u32 ale_entries; /* ale table size */ u32 bd_ram_size; /*buffer descriptor ram size */ - u32 rx_descs; /* Number of Rx Descriptios */ u32 mac_control; /* Mac control register */ u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ bool dual_emac; /* Enable Dual EMAC mode */ diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c index 18bf3a8..bcd9e45 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.c +++ b/drivers/net/ethernet/ti/davinci_cpdma.c @@ -543,6 +543,12 @@ struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, } EXPORT_SYMBOL_GPL(cpdma_chan_create); +int cpdma_chan_get_rx_buf_num(struct cpdma_ctlr *ctlr) +{ + return ctlr->pool->num_desc / 2; +} +EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num); + int cpdma_chan_destroy(struct cpdma_chan *chan) { struct cpdma_ctlr *ctlr; diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h b/drivers/net/ethernet/ti/davinci_cpdma.h index 86dee48..80c015c 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.h +++ b/drivers/net/ethernet/ti/davinci_cpdma.h @@ -81,6 +81,7 @@ int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr); struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, cpdma_handler_fn handler); +int cpdma_chan_get_rx_buf_num(struct cpdma_ctlr *ctlr); int cpdma_chan_destroy(struct cpdma_chan *chan); int cpdma_chan_start(struct cpdma_chan *chan); int cpdma_chan_stop(struct cpdma_chan *chan);