From patchwork Tue May 31 08:05:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 68908 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp1799601qge; Tue, 31 May 2016 01:10:33 -0700 (PDT) X-Received: by 10.66.121.197 with SMTP id lm5mr53906760pab.143.1464682231541; Tue, 31 May 2016 01:10:31 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id cy12si2901699pac.160.2016.05.31.01.10.31; Tue, 31 May 2016 01:10:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1162231AbcEaIK2 (ORCPT + 30 others); Tue, 31 May 2016 04:10:28 -0400 Received: from conuserg-12.nifty.com ([210.131.2.79]:25549 "EHLO conuserg-12.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756212AbcEaIGe (ORCPT ); Tue, 31 May 2016 04:06:34 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id u4V849MP022295; Tue, 31 May 2016 17:04:20 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com u4V849MP022295 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1464681861; bh=Xh7eqylMfCXTrPYl9Tco8/3bS24nPSasDja3TLL5gY0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UDpfxt2MG0ueJjQAXtkhteMyuRh/gCZ0LVcT3WS/13LON/rea634IkisQN/DS9Mgm QO+OlwUg3oN1xuLVR9uSXCh43RTv1sK3p+fAdvQcKi24aNcxvWNBdtzU+CxqrLLdmI LQ4geIzoHK/LYjfPg6AEW1wUExZ/SzN5ojfntg1RmmFJXVME9/DnYG1nHUF/aRBP27 8NfRZhoSgk+LK2r5vicyKLCv3cRIpyauNQ+ipTCRe7AR7Oadwi+rhlsz8q6hFZrU6y stm8rP8a49vvMLfUoAnBFppGN9U3aDrcU6C/IJ1l2ZoNfT/RiiueXIXB45S1P0c8qi Rz9CIO46b/3+w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-gpio@vger.kernel.org Cc: Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/17] pinctrl: uniphier: support per-pin input enable for new SoCs Date: Tue, 31 May 2016 17:05:17 +0900 Message-Id: <1464681923-7469-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464681923-7469-1-git-send-email-yamada.masahiro@socionext.com> References: <1464681923-7469-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit updates the core part for that. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 24 +++++++++++++----------- drivers/pinctrl/uniphier/pinctrl-uniphier.h | 1 + 2 files changed, 14 insertions(+), 11 deletions(-) -- 1.9.1 diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index ca2562a..d774a8e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -433,22 +433,24 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); + unsigned int reg, mask; - if (enable == 0) { - /* - * Multiple pins share one input enable, so per-pin disabling - * is impossible. - */ - dev_err(pctldev->dev, "unable to disable input\n"); + /* + * Multiple pins share one input enable, per-pin disabling is + * impossible. + */ + if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) && + !enable) return -EINVAL; - } + /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */ if (iectrl == UNIPHIER_PIN_IECTRL_NONE) - /* This pin is always input-enabled. nothing to do. */ - return 0; + return enable ? 0 : -EINVAL; + + reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4; + mask = BIT(iectrl % 32); - return regmap_update_bits(priv->regmap, UNIPHIER_PINCTRL_IECTRL, - BIT(iectrl), BIT(iectrl)); + return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); } static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 3fd5020..9941a4c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -166,6 +166,7 @@ struct uniphier_pinctrl_socdata { const struct uniphier_pinmux_function *functions; int functions_count; unsigned int caps; +#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1) #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0) };