From patchwork Wed May 11 14:15:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 67539 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp250763qge; Wed, 11 May 2016 07:18:20 -0700 (PDT) X-Received: by 10.66.221.167 with SMTP id qf7mr5341446pac.94.1462976300768; Wed, 11 May 2016 07:18:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z1si10158545pax.146.2016.05.11.07.18.20; Wed, 11 May 2016 07:18:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932263AbcEKOR7 (ORCPT + 29 others); Wed, 11 May 2016 10:17:59 -0400 Received: from mail-oi0-f47.google.com ([209.85.218.47]:34179 "EHLO mail-oi0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932147AbcEKOR5 (ORCPT ); Wed, 11 May 2016 10:17:57 -0400 Received: by mail-oi0-f47.google.com with SMTP id k142so69618778oib.1 for ; Wed, 11 May 2016 07:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=IusITjJKiAv29NpprYQMVrnlV7WN07QmxhEpuxTxNGw1X1YhdhpSQgsMV9NAGXS4mc n5ACkhUDROCkYhqj17fSTSv5cJyaAyKWQI4/nHv1t1wtYGvsJReQlasZp+c4fvzb+O/p mEoC29Nq1vMvYqM39Is/A/vbe0c3FSzNS91nk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=Flg8BQBiuZYwmmMEqbBf4Yd3EgiUDk2zCr08NGq+7aXcvHKJdsJwh2pxpYuC7F4kwl yUZeXdyEH8vmGRv9ftzrrMUJvZzyxKMrq+Uq4WNy8XWSZLas5B1SQgoLhNuyLNU8cr2Z 7CTBkG3PxbXIJjLHKX0Q2uib+WVXhITJBlZdEE3RrPDuDY8cTI3Mym5RRmb1NSqs4Dm/ zypWfUndxJ1GLUkow3wV6mb2fojmJibYBsQSJ0AHsxZdTcy6judzDKuS2DHD00ACMtMQ D+xMUWx2VrL4YAi7vxUuALCS3poZh79Ro9PdXY93SsYKKko+39S+HJ3/ldoT4Qjne+kg kkSw== X-Gm-Message-State: AOPr4FV1Yq9PIvO/rPDoy0e1m8TVfSw1Wxwm2f6GVGEtWX/H0Oo/odBOf5JKEJSk02EPXoUd X-Received: by 10.157.38.200 with SMTP id i8mr1959240otd.150.1462976276652; Wed, 11 May 2016 07:17:56 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:68a6:b401:fd49:9ae6]) by smtp.gmail.com with ESMTPSA id c2sm2232106obl.18.2016.05.11.07.17.56 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 11 May 2016 07:17:56 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Stephen Boyd , jilai wang , Andy Gross Subject: [Patch v4 3/8] firmware: qcom: scm: Use atomic SCM for cold boot Date: Wed, 11 May 2016 09:15:53 -0500 Message-Id: <1462976158-26016-4-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462976158-26016-1-git-send-email-andy.gross@linaro.org> References: <1462976158-26016-1-git-send-email-andy.gross@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch changes the cold_set_boot_addr function to use atomic SCM calls. cold_set_boot_addr required adding qcom_scm_call_atomic2 to support the two arguments going to the smc call. Using atomic removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross --- drivers/firmware/qcom_scm-32.c | 63 ++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 18 deletions(-) -- 1.9.1 Acked-by: Bjorn Andersson diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0883292..5be6a12 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -342,6 +342,41 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) return r0; } +/** + * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments + * @svc_id: service identifier + * @cmd_id: command identifier + * @arg1: first argument + * @arg2: second argument + * + * This shall only be used with commands that are guaranteed to be + * uninterruptable, atomic and SMP safe. + */ +static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) +{ + int context_id; + + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; + + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + __asmeq("%4", "r3") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); + return r0; +} + u32 qcom_scm_get_version(void) { int context_id; @@ -378,22 +413,6 @@ u32 qcom_scm_get_version(void) } EXPORT_SYMBOL(qcom_scm_get_version); -/* - * Set the cold/warm boot address for one of the CPU cores. - */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) -{ - struct { - __le32 flags; - __le32 addr; - } cmd; - - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); -} - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -423,7 +442,8 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + flags, virt_to_phys(entry)); } /** @@ -439,6 +459,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) int ret; int flags = 0; int cpu; + struct { + __le32 flags; + __le32 addr; + } cmd; /* * Reassign only if we are switching from hotplug entry point @@ -454,7 +478,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + cmd.addr = cpu_to_le32(virt_to_phys(entry)); + cmd.flags = cpu_to_le32(flags); + ret = qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry;