From patchwork Fri Apr 22 17:14:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 66479 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp839610qge; Fri, 22 Apr 2016 10:16:06 -0700 (PDT) X-Received: by 10.98.48.199 with SMTP id w190mr13243916pfw.18.1461345365116; Fri, 22 Apr 2016 10:16:05 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id qm9si8593874pac.165.2016.04.22.10.16.04; Fri, 22 Apr 2016 10:16:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932601AbcDVRQB (ORCPT + 29 others); Fri, 22 Apr 2016 13:16:01 -0400 Received: from mail-ig0-f175.google.com ([209.85.213.175]:37441 "EHLO mail-ig0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932445AbcDVROn (ORCPT ); Fri, 22 Apr 2016 13:14:43 -0400 Received: by mail-ig0-f175.google.com with SMTP id g8so22151325igr.0 for ; Fri, 22 Apr 2016 10:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bodst3gCV4bnGomHtdzv+kHhQRuYg4POW1vZ6g23G7E=; b=H57bqBl4l09t9Mro+HL5UqFBAzSOvaBZckR9uAgu0qCa4hvwjz1A0oMhWKszlErNeR 1ohyrsV53HUJUQW1TTUufKQHlfuh/KBzbmTWDPffLBu6A5sttwCp9FuQJXyZrIOE2fXg xJYLR3ccSzW8JalLDL70Ld0m/tzpD7cML7c4A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bodst3gCV4bnGomHtdzv+kHhQRuYg4POW1vZ6g23G7E=; b=W52Jdy0w1dM/87Ez42nv9SIC3d1Kc0Yn0UK62mVUHYIJPdaGN530rKTSggTrhg5GNc XoOTjGTD7/8Ln62lPqeVY/f6laqzCUEckfZei4F7irTs5T3zW6BYVMALTHgtfTC7X5GK 9f+LBT1Puguh3/LBtPocD7USeluqZyg5qjZJ1BB31iHkb9k6/7UM+RerzHLWuwT2mCfA hGOC1zqr4mBVQ8yOE4uy+o65knsyBXkvhpoYISNpAR0Os/2M/TqHMVV599snUn6ewDqS cKHRZuY/RTt7aVKBaSjuH9K4seS3ZLNgAdDRcdIxrRl4+VZoiRDk0QAcQ5m8fl4YRAMM fS7g== X-Gm-Message-State: AOPr4FVfbnQ/ddInItw5KL3TP7NJLDuDgUbciAZcOpYT7+pMHkQddbmBsbLEoF3KDO0hx4Xk X-Received: by 10.50.170.8 with SMTP id ai8mr5413279igc.41.1461345282712; Fri, 22 Apr 2016 10:14:42 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id vg8sm1975886igb.15.2016.04.22.10.14.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 Apr 2016 10:14:41 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, Suzuki.Poulose@arm.com Cc: linux-kernel@vger.kernel.org Subject: [PATCH V3 14/18] coresight: tmc: keep track of memory width Date: Fri, 22 Apr 2016 11:14:11 -0600 Message-Id: <1461345255-11758-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1461345255-11758-1-git-send-email-mathieu.poirier@linaro.org> References: <1461345255-11758-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Accessing the HW configuration register each time the memory width is needed simply doesn't make sense. It is much more efficient to read the value once and keep a reference for later use. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 14 +--------- drivers/hwtracing/coresight/coresight-tmc.c | 34 +++++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 10 +++++--- 3 files changed, 41 insertions(+), 17 deletions(-) -- 2.5.0 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index cc88c15ba45c..981c5ca75e36 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -41,25 +41,13 @@ void tmc_etb_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) { - enum tmc_mem_intf_width memwidth; - u8 memwords; char *bufp; u32 read_data; int i; - memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10); - if (memwidth == TMC_MEM_INTF_WIDTH_32BITS) - memwords = 1; - else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS) - memwords = 2; - else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS) - memwords = 4; - else - memwords = 8; - bufp = drvdata->buf; while (1) { - for (i = 0; i < memwords; i++) { + for (i = 0; i < drvdata->memwidth; i++) { read_data = readl_relaxed(drvdata->base + TMC_RRD); if (read_data == 0xFFFFFFFF) return; diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 55806352b1f1..cb030a09659d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -193,6 +193,39 @@ static const struct file_operations tmc_fops = { .llseek = no_llseek, }; +static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid) +{ + enum tmc_mem_intf_width memwidth; + + /* + * Excerpt from the TRM: + * + * DEVID::MEMWIDTH[10:8] + * 0x2 Memory interface databus is 32 bits wide. + * 0x3 Memory interface databus is 64 bits wide. + * 0x4 Memory interface databus is 128 bits wide. + * 0x5 Memory interface databus is 256 bits wide. + */ + switch (BMVAL(devid, 8, 10)) { + case 0x2: + memwidth = TMC_MEM_INTF_WIDTH_32BITS; + break; + case 0x3: + memwidth = TMC_MEM_INTF_WIDTH_64BITS; + break; + case 0x4: + memwidth = TMC_MEM_INTF_WIDTH_128BITS; + break; + case 0x5: + memwidth = TMC_MEM_INTF_WIDTH_256BITS; + break; + default: + memwidth = 0; + } + + return memwidth; +} + #define coresight_tmc_simple_func(name, offset) \ coresight_simple_func(struct tmc_drvdata, name, offset) @@ -306,6 +339,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); + drvdata->memwidth = tmc_get_memwidth(devid); if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { if (np) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 9b4c215d2b6b..12a097f3d06c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -81,10 +81,10 @@ enum tmc_mode { }; enum tmc_mem_intf_width { - TMC_MEM_INTF_WIDTH_32BITS = 0x2, - TMC_MEM_INTF_WIDTH_64BITS = 0x3, - TMC_MEM_INTF_WIDTH_128BITS = 0x4, - TMC_MEM_INTF_WIDTH_256BITS = 0x5, + TMC_MEM_INTF_WIDTH_32BITS = 1, + TMC_MEM_INTF_WIDTH_64BITS = 2, + TMC_MEM_INTF_WIDTH_128BITS = 4, + TMC_MEM_INTF_WIDTH_256BITS = 8, }; /** @@ -101,6 +101,7 @@ enum tmc_mem_intf_width { * @size: @buf size. * @mode: how this TMC is being used. * @config_type: TMC variant, must be of type @tmc_config_type. + * @memwidth: width of the memory interface databus, in bytes. * @trigger_cntr: amount of words to store after a trigger. */ struct tmc_drvdata { @@ -117,6 +118,7 @@ struct tmc_drvdata { u32 size; local_t mode; enum tmc_config_type config_type; + enum tmc_mem_intf_width memwidth; u32 trigger_cntr; };