From patchwork Thu Apr 21 02:04:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 66273 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2776384qge; Wed, 20 Apr 2016 19:04:56 -0700 (PDT) X-Received: by 10.98.95.4 with SMTP id t4mr16915332pfb.100.1461204296317; Wed, 20 Apr 2016 19:04:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bw8si461830pad.127.2016.04.20.19.04.56; Wed, 20 Apr 2016 19:04:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751742AbcDUCEy (ORCPT + 29 others); Wed, 20 Apr 2016 22:04:54 -0400 Received: from conuserg-11.nifty.com ([210.131.2.78]:31367 "EHLO conuserg-11.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751520AbcDUCEx (ORCPT ); Wed, 20 Apr 2016 22:04:53 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id u3L23SOM012326; Thu, 21 Apr 2016 11:03:29 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com u3L23SOM012326 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1461204209; bh=n+mLayU0YegqxB6QlFx50k7u8s4ybhSL6ya/2nwvZLM=; h=From:To:Cc:Subject:Date:From; b=0FAIJJma778ioK0EtkBfgjZiX20e+/JFTIqnxt9jhXDyibqNzWiDn08psFXI6sMJ6 1isvPl02zJWu+YOxja97bOHWrxZ5j/bGgDcaVPf21dlCKp4c7Vs1RvF9JKFy/eq1yZ opSuOlmIKajJ5onxvICrO/yUHagYxpIlp9LcDrXMpoVQ3Gp7TQDXUh/l/1WKQUxs8d dqEz6RJLKVA8ohRRq4d1u6WqfZH6FL8ZOg+h4zEju5IaiVNhSkdRhUJf8xj47ZXCqq x6O3q0o4Jqd8CHUUZ0Bk0f7Y7eI5ubCzDtoQEpwPjXsxj7r/80ZsbZIMSJoo8V5p8F 3xNyiMB9GPdJw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: patches@arm.linux.org.uk Cc: Masahiro Yamada , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs Date: Thu, 21 Apr 2016 11:04:20 +0900 Message-Id: <1461204260-27202-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two possible ways to achieve this: [1] Each CPU initializes active ways for itself. This can be done via the SSCLPDAWCR register. This is a banked register, so each CPU sees a different instance of the register for its own. [2] The master CPU initializes active ways for all the CPUs. This is available via SSCDAWCARMR(N) registers, where all instances of SSCLPDAWCR are mirrored. They are mapped at the address SSCDAWCARMR + 4 * N, where N is the CPU number. The outer cache frame work does not support a per-CPU init callback. So this commit adopts [2]; the master CPU iterates over possible CPUs setting up SSCDAWCARMR(N) registers. Signed-off-by: Masahiro Yamada --- KernelVersion: 4.6-rc4 arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c index a6fa7b7..c8e2f49 100644 --- a/arch/arm/mm/cache-uniphier.c +++ b/arch/arm/mm/cache-uniphier.c @@ -96,6 +96,7 @@ struct uniphier_cache_data { void __iomem *ctrl_base; void __iomem *rev_base; void __iomem *op_base; + void __iomem *way_ctrl_base; u32 way_present_mask; u32 way_locked_mask; u32 nsets; @@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways( struct uniphier_cache_data *data, u32 way_mask) { + unsigned int cpu; + data->way_locked_mask = way_mask & data->way_present_mask; - writel_relaxed(~data->way_locked_mask & data->way_present_mask, - data->ctrl_base + UNIPHIER_SSCLPDAWCR); + for_each_possible_cpu(cpu) + writel_relaxed(~data->way_locked_mask & data->way_present_mask, + data->way_ctrl_base + 4 * cpu); } static void uniphier_cache_maint_range(unsigned long start, unsigned long end, @@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np, goto err; } + data->way_ctrl_base = data->ctrl_base + 0xc00; + if (*cache_level == 2) { u32 revision = readl(data->rev_base + UNIPHIER_SSCID); /* @@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np, */ if (revision <= 0x16) data->range_op_max_size = (u32)1 << 22; + + /* + * Unfortunatly, the offset address of active way control base + * varies from SoC to SoC. + */ + switch (revision) { + case 0x11: /* sLD3 */ + data->way_ctrl_base = data->ctrl_base + 0x870; + break; + case 0x12: /* LD4 */ + case 0x16: /* sld8 */ + data->way_ctrl_base = data->ctrl_base + 0x840; + break; + default: + break; + } } data->range_op_max_size -= data->line_size;