From patchwork Sat Apr 16 11:03:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 65978 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp383113qge; Sat, 16 Apr 2016 04:04:44 -0700 (PDT) X-Received: by 10.98.102.15 with SMTP id a15mr30354927pfc.90.1460804684005; Sat, 16 Apr 2016 04:04:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id zv5si3084822pac.220.2016.04.16.04.04.43; Sat, 16 Apr 2016 04:04:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751308AbcDPLEg (ORCPT + 29 others); Sat, 16 Apr 2016 07:04:36 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:15856 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751213AbcDPLEf (ORCPT ); Sat, 16 Apr 2016 07:04:35 -0400 Received: from 172.24.1.51 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.51]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DIW18448; Sat, 16 Apr 2016 19:04:06 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.47.90.94) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Sat, 16 Apr 2016 19:03:56 +0800 From: Gabriele Paoloni To: , CC: , , , , Subject: [PATCH v2] PCI: Designware: remove wrong RC memory base/limit configuration Date: Sat, 16 Apr 2016 12:03:39 +0100 Message-ID: <1460804619-2972-1-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.47.90.94] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.57121C28.008F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8ab6d6f0209a1707a8ed71ab673220bc Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently dw_pcie_setup_rc configures memory base and memory limit in the type1 configuration header for the root complex. In doing so it uses the cpu address (pp->mem_base) rather than the bus address (pp->mem_bus_addr): this is wrong and it is useless since the configuration is overwritten later on when pci_bus_assign_resources() is called. Therefore this patch just removes this configuration from dw_pcie_setup_rc. Signed-off-by: Gabriele Paoloni --- v1 -> v2 : removed unused variables in dw_pcie_setup_rc() --- drivers/pci/host/pcie-designware.c | 8 -------- 1 file changed, 8 deletions(-) -- 2.1.4 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index a4cccd3..e3cb1f9 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -728,8 +728,6 @@ static struct pci_ops dw_pcie_ops = { void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; - u32 membase; - u32 memlimit; /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); @@ -788,12 +786,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= 0x00010100; dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); - /* setup memory base, memory limit */ - membase = ((u32)pp->mem_base & 0xfff00000) >> 16; - memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000; - val = memlimit | membase; - dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); - /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000;