From patchwork Fri Apr 15 10:30:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 65890 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1097795qge; Fri, 15 Apr 2016 03:31:20 -0700 (PDT) X-Received: by 10.98.17.78 with SMTP id z75mr28704111pfi.40.1460716280459; Fri, 15 Apr 2016 03:31:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v185si4033409pfb.245.2016.04.15.03.31.20; Fri, 15 Apr 2016 03:31:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751787AbcDOKbS (ORCPT + 29 others); Fri, 15 Apr 2016 06:31:18 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:60914 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751075AbcDOKbO (ORCPT ); Fri, 15 Apr 2016 06:31:14 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id u3FATub2009661; Fri, 15 Apr 2016 19:30:00 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u3FATub2009661 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1460716201; bh=rCMGxAm3KdD6VpYWpjXKw4Tqwr0YfN02uTzANlddAGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qT+2boynLgiBCybG0m6Wo9pUNtbrViZ1YosFgWU9qJ6rLOlvwL1i0uBjJcRKKq62I 2WRsSHDm3g0vu9Q8qrJSKVh6OiuFJ+9UBTAz8OZEDuRY4dJFFgKnIidxwbbulICOTP Eb3CoF/ySQw+I2I22KVAS3sv8wr//RON1/1TkdGOMDbJm9edXChRD6fjFonoXtZEnD AhE7wvAqvvq7nG8l/7PJ0bn7xVQhjYXCiFMCZZHi2pATuMRbVtsEdlBwh4oMCv7eAA dNbXF2wOUmSr4Jcv0ihGRaJUO9xeE9Ahi//MWhMrWIlVa9/jCUndXzOCPkZ8Hj2AYu kRoY3RBpBCKnA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: arm@kernel.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, Kumar Gala , linux-kernel@vger.kernel.org, Ian Campbell , Rob Herring , Pawel Moll , Will Deacon , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table Date: Fri, 15 Apr 2016 19:30:47 +0900 Message-Id: <1460716247-28049-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460716247-28049-1-git-send-email-yamada.masahiro@socionext.com> References: <1460716247-28049-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 8-byte register located at 0x59801200 on this SoC is dedicated for waking up secondary CPUs. We can use it and save normal memory. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.9.1 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index 651c9d9..f73b09e 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -77,7 +77,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x59801200>; }; cpu1: cpu@1 { @@ -85,7 +85,7 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x59801200>; }; cpu2: cpu@100 { @@ -93,7 +93,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x59801200>; }; cpu3: cpu@101 { @@ -101,7 +101,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; enable-method = "spin-table"; - cpu-release-addr = <0 0x80000100>; + cpu-release-addr = <0 0x59801200>; }; };