From patchwork Fri Apr 15 07:05:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 65870 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1020869qge; Fri, 15 Apr 2016 00:06:23 -0700 (PDT) X-Received: by 10.98.64.4 with SMTP id n4mr27314613pfa.58.1460703982510; Fri, 15 Apr 2016 00:06:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id hq1si3341199pac.56.2016.04.15.00.06.22; Fri, 15 Apr 2016 00:06:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752866AbcDOHGO (ORCPT + 29 others); Fri, 15 Apr 2016 03:06:14 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:49992 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751127AbcDOHGI (ORCPT ); Fri, 15 Apr 2016 03:06:08 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u3F74oNx030038; Fri, 15 Apr 2016 16:04:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u3F74oNx030038 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1460703891; bh=mnkjUUY99ZcIYTMi8gA+sqx2w9qdOTTPpl7srIL7bm4=; h=From:To:Cc:Subject:Date:From; b=qskKM6J/m9cRYudlcPUF/PFhU0qpJhleAFOZPdO4HlUjW3+q48IgNPGTQ/48ek1Dp CqXbA64CZdNAzWlc080Zhc+1OMNZIwPVQzv1xG2KSAKDlE9NKOmTNfNPwxY18D773b PpFzYDQaz7S6utOoXoPx0wzYQ44ky/r5Y0PC03uPiefDpsjIwwcnF9ryrS8YaKciVY saHOGiCa5ChGTp/qG0HQhCV8WDh0FlQlOKXNuJUNALs3QngeI7aLwztWpTt8rlSCad b9ncpqj9ukK60kkUXmLA7ypMaZgB/5FqX8kZ4zFJpZ/8OZE8nsz7mVLfpai25KCw70 aOZ0Y2hVm9V7w== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs Date: Fri, 15 Apr 2016 16:05:46 +0900 Message-Id: <1460703947-12539-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two possible ways to achieve this: [1] Each CPU initializes active ways for itself. This can be done via the SSCLPDAWCR register. This is a banked register, so each CPU sees a different instance of the register. [2] The master CPU initializes active ways for all the CPUs. This is available via SSCDAWCARMR(N) registers. They are mapped at the address SSCDAWCARMR + 4 * N, where N is the CPU number. Currently, the outer cache frame work does not support a per-CPU init callback. So this commit adopts [2]; the master CPU iterates over possible CPUs setting up SSCDAWCARMR(N) registers. Unfortunately, the register offsets of SSCDAWCARMR(N) are different by SoC. We can live with it by checking the version register. Signed-off-by: Masahiro Yamada --- arch/arm/mm/cache-uniphier.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c index a6fa7b7..c8e2f49 100644 --- a/arch/arm/mm/cache-uniphier.c +++ b/arch/arm/mm/cache-uniphier.c @@ -96,6 +96,7 @@ struct uniphier_cache_data { void __iomem *ctrl_base; void __iomem *rev_base; void __iomem *op_base; + void __iomem *way_ctrl_base; u32 way_present_mask; u32 way_locked_mask; u32 nsets; @@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways( struct uniphier_cache_data *data, u32 way_mask) { + unsigned int cpu; + data->way_locked_mask = way_mask & data->way_present_mask; - writel_relaxed(~data->way_locked_mask & data->way_present_mask, - data->ctrl_base + UNIPHIER_SSCLPDAWCR); + for_each_possible_cpu(cpu) + writel_relaxed(~data->way_locked_mask & data->way_present_mask, + data->way_ctrl_base + 4 * cpu); } static void uniphier_cache_maint_range(unsigned long start, unsigned long end, @@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np, goto err; } + data->way_ctrl_base = data->ctrl_base + 0xc00; + if (*cache_level == 2) { u32 revision = readl(data->rev_base + UNIPHIER_SSCID); /* @@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np, */ if (revision <= 0x16) data->range_op_max_size = (u32)1 << 22; + + /* + * Unfortunatly, the offset address of active way control base + * varies from SoC to SoC. + */ + switch (revision) { + case 0x11: /* sLD3 */ + data->way_ctrl_base = data->ctrl_base + 0x870; + break; + case 0x12: /* LD4 */ + case 0x16: /* sld8 */ + data->way_ctrl_base = data->ctrl_base + 0x840; + break; + default: + break; + } } data->range_op_max_size -= data->line_size;