From patchwork Tue Apr 12 23:55:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 65669 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2204904qge; Tue, 12 Apr 2016 16:59:20 -0700 (PDT) X-Received: by 10.98.71.156 with SMTP id p28mr8511504pfi.139.1460505560473; Tue, 12 Apr 2016 16:59:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u27si12553635pfi.159.2016.04.12.16.59.20; Tue, 12 Apr 2016 16:59:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030604AbcDLX7N (ORCPT + 29 others); Tue, 12 Apr 2016 19:59:13 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:34951 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030360AbcDLX7J (ORCPT ); Tue, 12 Apr 2016 19:59:09 -0400 Received: by mail-pa0-f49.google.com with SMTP id fs9so3607916pac.2 for ; Tue, 12 Apr 2016 16:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DjHS67T4wXF+0b812qjoYEg2UqvYEBtDymtH/J1o3hY=; b=csiQKmhfKciBjds89Jo9QSjD7+KC/4A5ha6a+li4MR0/t3qUyja2Hkj0FIrA0hxdTu kXYRheJtbHWWWApWnnUWNdxyFWvitlduA9TgAuuiqG64v5Sp/R0Fqg/Np+stTCqPI0a6 gi4NnOI4Us6YRn6CEe4NjlBI7i06minkJDMOg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DjHS67T4wXF+0b812qjoYEg2UqvYEBtDymtH/J1o3hY=; b=nLWQjlRgi8Es3Fll54fPNwaG3xCO/S6wuW1JGCVLbjz+2R9lyeM3tLTL6jB5OLjEa4 Io4D/vmv4APiGenbl0OhVs1NNHY0jCHO8bHb57rsiw/RLFRMfM6ZHo7sRdD6jNTEfC0h 3LkinL2vcwecsSvk/7emlXx4OhdU9+HmtsBDRLRqLNUX5hFg+/knHc+nPEbBsfZhMC8E okVJzwoAVQ5N26e+w/7WG3P8OGApXfV+f1Uxw5nmO0+WDVGIDZvfbnlN/aan9v8VRlHW XieyE1sC8lDiisDHFsCkFcuP/vJ9QY79jPAed+V1Ycaof+mD+HL4q/rDTpsp30+wsoow Y0lg== X-Gm-Message-State: AOPr4FVdYeGlNu8gBHWAzHz2FGWDAdEzN+ljyr6MGkW9FMj8l1TitpR2upGlT0i3k6mPocGB X-Received: by 10.66.221.167 with SMTP id qf7mr8539795pac.94.1460505548471; Tue, 12 Apr 2016 16:59:08 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.226]) by smtp.gmail.com with ESMTPSA id i1sm46165795pfj.17.2016.04.12.16.58.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Apr 2016 16:59:07 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, will.deacon@arm.com, haojian.zhuang@linaro.org, linus.walleij@linaro.org, tony@atomide.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leo Yan Subject: [PATCH v4 11/16] arm64: dts: add Hi6220's stub clock node Date: Wed, 13 Apr 2016 07:55:47 +0800 Message-Id: <1460505352-13157-12-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460505352-13157-1-git-send-email-guodong.xu@linaro.org> References: <1460505352-13157-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan Enable SRAM node and stub clock node for Hi6220, which uses mailbox channel 1 for CPU's frequency change. Furthermore, add the CPU clock phandle in CPU's node and using operating-points-v2 to register operating points. So can be used by cpufreq-dt driver. Signed-off-by: Leo Yan Acked-by: Jassi Brar Acked-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index d71c51f..3a665ef 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -82,6 +82,11 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&stub_clock 0>; + operating-points-v2 = <&cpu_opp_table>; + cooling-min-level = <4>; + cooling-max-level = <0>; + #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -90,6 +95,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -98,6 +104,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -106,6 +113,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -114,6 +122,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -122,6 +131,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -130,6 +140,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -138,10 +149,42 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <729000000>; + opp-microvolt = <1090000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1180000>; + clock-latency-ns = <500000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1330000>; + clock-latency-ns = <500000>; + }; + }; + gic: interrupt-controller@f6801000 { compatible = "arm,gic-400"; reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ @@ -169,6 +212,11 @@ #size-cells = <2>; ranges; + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; + ao_ctrl: ao_ctrl@f7800000 { compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; @@ -194,6 +242,14 @@ #clock-cells = <1>; }; + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mbox-names = "mbox-tx"; + mboxes = <&mailbox 1 0 11>; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>;