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[92.17.247.99]) by smtp.gmail.com with ESMTPSA id gt7sm32431907wjc.1.2016.04.12.02.34.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Apr 2016 02:34:42 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross , linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-soc@vger.kernel.org, srinivas.kandagatla@linaro.org Subject: [PATCH v2 04/13] ARM: dts: db600c: add board support with serial Date: Tue, 12 Apr 2016 10:33:53 +0100 Message-Id: <1460453642-5809-5-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1460453642-5809-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1460453642-5809-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support to DB600c with basic serial ports. DB600c is based on APQ8064. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts | 36 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts -- 2.5.0 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 95c1923..fef61b3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -539,6 +539,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-arrow-db600c.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-yuga.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts new file mode 100644 index 0000000..57d4500 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -0,0 +1,36 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "Arrow Electronics, APQ8064 DB600c"; + compatible = "arrow,db600c", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi1_serial; + }; + + soc { + gsbi@12440000 { + status = "okay"; + qcom,mode = ; + serial@12450000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi1_uart_4pins>; + }; + }; + + /* DEBUG UART */ + gsbi@16600000 { + status = "okay"; + qcom,mode = ; + serial@16640000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + }; + }; + }; +};