From patchwork Thu Apr 7 02:51:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 65226 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp216644lbc; Wed, 6 Apr 2016 19:53:40 -0700 (PDT) X-Received: by 10.98.79.203 with SMTP id f72mr1154188pfj.102.1459997619753; Wed, 06 Apr 2016 19:53:39 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 78si8421244pft.93.2016.04.06.19.53.39; Wed, 06 Apr 2016 19:53:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754978AbcDGCx2 (ORCPT + 29 others); Wed, 6 Apr 2016 22:53:28 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:35265 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754872AbcDGCxZ (ORCPT ); Wed, 6 Apr 2016 22:53:25 -0400 Received: by mail-pf0-f182.google.com with SMTP id n1so46035398pfn.2 for ; Wed, 06 Apr 2016 19:53:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=KfVwSQPQ5f3KOA4afVdND4MGO49xZ7XIqqVVbUFPWdXsarUZ6AJP8VoAX/V+HcgSWU FFtdPPHxQUgei3CjpImJI3/ikpM7UsBb53z8c3nOANH2fh1v+T7d5ujZIRJfSpdUGe0t JTOQ/RA5+KIhQIZtal//9KZJAfQCOouGrK0XU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=LhPh3xuRAsbvCa1oBbSGoCUqqgDrDb8k98CXIsQ6Yu5XwyIEmv5k/DFlNd9lEjjIDs qjAPBSdI1N8fAvr5F+/R59LSWrfdNGfFckE+BlrW7WjXe2qITQp08KNp6gUblcGmOoBs +ZIe49AIHUlC7QFctvcK8uYYR4wSxecaz35wwrEFgX/HkqB6l6QIkGa8oKYQZ46nvuxc 2odNzJMRKnkHgSgZ1XyF2rK2Lh+N9M9XM8UtBfwGqRnFAMGmaBjyEKCVlHbW7zCqtQD5 MktxzCWvz3lM+w6JJMm3oRHeBvRObAM1lzfcoPv7HMpgFBFUB0pL9jmvvsZk5smygv/c B6GA== X-Gm-Message-State: AD7BkJIxSxdSCDo01tbkmsuXbMD/Cd1txkbo1fRf5PCuLq09gyTEO038hWYb3qEHp5EV/qN0 X-Received: by 10.98.76.194 with SMTP id e63mr1104790pfj.89.1459997604331; Wed, 06 Apr 2016 19:53:24 -0700 (PDT) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id xa4sm7829736pab.26.2016.04.06.19.53.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Apr 2016 19:53:23 -0700 (PDT) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Cc: mike.leach@arm.com, Michael.Williams@arm.com, al.grant@arm.com, tor@ti.com, nicolas.guion@st.com, pratikp@codeaurora.org, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH V5 3/4] coresight-stm: Bindings for System Trace Macrocell Date: Thu, 7 Apr 2016 10:51:18 +0800 Message-Id: <1459997479-19431-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459997479-19431-1-git-send-email-zhang.chunyan@linaro.org> References: <1459997479-19431-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.