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[209.132.180.67]) by mx.google.com with ESMTP id l77si1632668pfb.252.2016.04.05.06.31.14; Tue, 05 Apr 2016 06:31:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933230AbcDENbG (ORCPT + 29 others); Tue, 5 Apr 2016 09:31:06 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:35229 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932571AbcDENbA (ORCPT ); Tue, 5 Apr 2016 09:31:00 -0400 Received: by mail-pf0-f175.google.com with SMTP id n1so11019615pfn.2 for ; Tue, 05 Apr 2016 06:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vezP6NJjual5Bn0wnxQMfdhpkQZGZQmX/S8bG4By5Sw=; b=Ntq0G47SxC22E55II6mk/WzYiLREkoIgTPc6xEpfZ/7XsYqeOYQaZL9zMODApuBSjT K1Egvwb3rLWFcxlhwxPNfh/Rlo5wLgQ7wgTcFdTWD5dFFnBb650GHoKOAf1Ry1uKBFkP 4Pyuk8P9Tkem30j4aVY2uZieTraERyM4lyvjI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vezP6NJjual5Bn0wnxQMfdhpkQZGZQmX/S8bG4By5Sw=; b=XTvdoVAe/ijzImaELrCNnxftkhckF8dgE6dliV8e8z1ZDDetSd1yc5+hMaPWpR6oPi dxNhONIBpdDZwkUVpF6vJPvQoXBtUntiP3oBRDtOp0Wwko/DiCXB7rY/DcebkPmL2xwb 6LxEMxclRWdIF8caqUfoOp3C1jxoAdvaMY16tRZgXpOWLZ50LxSj66hC6o/END5X+CbL 84LivRCq0l9rLwZBf+y95XD5YEAA+/RWBIGLDYo0RdC96vvtxQpXpcBXkH+QUVjqAv+3 BSCzW2/6s0BuA+7KMCjWTk+P47L2u8kX2JJJx001RzAnmv5b3WtoCW9G02KUri9zPzsl iW/Q== X-Gm-Message-State: AD7BkJL0tUNYkKqIArlqrPwY5L5OAwHkaCDtYsS0cJK7TxaKI67LyTfE2rmgJRLEIrMe8oNb X-Received: by 10.98.71.91 with SMTP id u88mr29720606pfa.161.1459863058875; Tue, 05 Apr 2016 06:30:58 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.49]) by smtp.gmail.com with ESMTPSA id wh9sm8060481pab.8.2016.04.05.06.30.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Apr 2016 06:30:58 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, mark.rutland@arm.com, robh@kernel.org, grant.likely@secretlab.ca, linus.walleij@linaro.org, arnd.bergmann@linaro.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kong.kongxinwei@hisilicon.com, Leo Yan Subject: [PATCH v3 11/16] arm64: dts: add Hi6220's stub clock node Date: Tue, 5 Apr 2016 21:27:35 +0800 Message-Id: <1459862860-9775-12-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459862860-9775-1-git-send-email-guodong.xu@linaro.org> References: <1459862860-9775-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan Enable SRAM node and stub clock node for Hi6220, which uses mailbox channel 1 for CPU's frequency change. Furthermore, add the CPU clock phandle in CPU's node and using operating-points-v2 to register operating points. So can be used by cpufreq-dt driver. Signed-off-by: Leo Yan Acked-by: Jassi Brar Acked-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 6cddd47..2442617 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -82,6 +82,11 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&stub_clock 0>; + operating-points-v2 = <&cpu_opp_table>; + cooling-min-level = <4>; + cooling-max-level = <0>; + #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -90,6 +95,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -98,6 +104,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -106,6 +113,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -114,6 +122,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -122,6 +131,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -130,6 +140,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; @@ -138,10 +149,42 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <729000000>; + opp-microvolt = <1090000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1180000>; + clock-latency-ns = <500000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1330000>; + clock-latency-ns = <500000>; + }; + }; + gic: interrupt-controller@f6801000 { compatible = "arm,gic-400"; reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ @@ -169,6 +212,11 @@ #size-cells = <2>; ranges; + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; + ao_ctrl: ao_ctrl@f7800000 { compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; @@ -194,6 +242,14 @@ #clock-cells = <1>; }; + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mbox-names = "mbox-tx"; + mboxes = <&mailbox 1 0 11>; + }; + uart0: uart@f8015000 { /* console */ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>;