From patchwork Mon Apr 4 11:37:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 64985 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1133510lbc; Mon, 4 Apr 2016 04:38:36 -0700 (PDT) X-Received: by 10.66.146.39 with SMTP id sz7mr53129485pab.76.1459769914683; Mon, 04 Apr 2016 04:38:34 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fv2si19894835pad.86.2016.04.04.04.38.34; Mon, 04 Apr 2016 04:38:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755379AbcDDLiQ (ORCPT + 29 others); Mon, 4 Apr 2016 07:38:16 -0400 Received: from foss.arm.com ([217.140.101.70]:44543 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755336AbcDDLiJ (ORCPT ); Mon, 4 Apr 2016 07:38:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D020556; Mon, 4 Apr 2016 04:36:58 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51EED3F50D; Mon, 4 Apr 2016 04:38:06 -0700 (PDT) From: Julien Grall To: kvmarm@lists.cs.columbia.edu Cc: christoffer.dall@linaro.org, marc.zyngier@arm.com, fu.wei@linaro.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wei@redhat.com, al.stone@linaro.org, gg@slimlogic.co.uk, Julien Grall , Thomas Gleixner , Jason Cooper Subject: [PATCH v5 3/9] irqchip/gic-v2: Gather ACPI specific data in a single structure Date: Mon, 4 Apr 2016 12:37:34 +0100 Message-Id: <1459769860-6629-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459769860-6629-1-git-send-email-julien.grall@arm.com> References: <1459769860-6629-1-git-send-email-julien.grall@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ACPI code requires to use global variables in order to collect information from the tables. For now, a single global variable is used, but more will be added in a subsequent patch. To make clear they are ACPI specific, gather all the information in a single structure. Signed-off-by: Julien Grall Acked-by: Christofer Dall --- Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Changes in v4: - Update commit message - Rename cpu_phy_base to cpu_phys_base - Add Christopher's acked-by Changes in v2: - Patch added --- drivers/irqchip/irq-gic.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 1.9.1 Acked-by: Hanjun Guo diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 282344b..7a73786 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1245,7 +1245,10 @@ IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); #endif #ifdef CONFIG_ACPI -static phys_addr_t cpu_phy_base __initdata; +static struct +{ + phys_addr_t cpu_phys_base; +} acpi_data __initdata; static int __init gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, @@ -1265,10 +1268,10 @@ gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, * All CPU interface addresses have to be the same. */ gic_cpu_base = processor->base_address; - if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) + if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) return -EINVAL; - cpu_phy_base = gic_cpu_base; + acpi_data.cpu_phys_base = gic_cpu_base; cpu_base_assigned = 1; return 0; } @@ -1316,7 +1319,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, return -EINVAL; } - cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); + cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); if (!cpu_base) { pr_err("Unable to map GICC registers\n"); return -ENOMEM;