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[209.132.180.67]) by mx.google.com with ESMTP id u86si26679658pfa.250.2016.04.02.02.31.58; Sat, 02 Apr 2016 02:31:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753943AbcDBJbo (ORCPT + 29 others); Sat, 2 Apr 2016 05:31:44 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:35195 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752809AbcDBJbm (ORCPT ); Sat, 2 Apr 2016 05:31:42 -0400 Received: by mail-pf0-f174.google.com with SMTP id n1so3541689pfn.2 for ; Sat, 02 Apr 2016 02:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dmhj3oTzwWV6V112acOBiMZwT/ZQZpHSmHVExDH92BI=; b=U969gRhbtSCQAFx4C+aD3EQxwxZQ0g22bsM5I/q7p1tOalI4RHudngRX/tuVtqz1uw 5bKM3jNbjOZaYEpqrubBa0kj35eoXqtu6cObZIqR/hhkCxIEPR20nyGCUwNZ3IZJ1z9d w8n+ZW0hmSbn6Gut3k4MRdWTL5xC8VwC/Hurc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dmhj3oTzwWV6V112acOBiMZwT/ZQZpHSmHVExDH92BI=; b=OYeuJqi5UXv+NJ18oOKVs+tSceSsoqfMWDbAamE0ppNAbAoP8qWbQciGRA8OQmlONO Iou/KIaMFC4c2ACT8XmCiO1csZ7UDQcYURdZ9ESSNx2nsC4tLg1BvXM0urNxTKv5fA/w 00O0oynWQ+cPK/igB9nWITpy7qQXKNRuR9hKZLTVto06VWqjMPkuuCYIx4sbruQmy1mL Fe2DYMeL/k8AXePPMke3Ivo2qfVL69nKkUSUHYpXSpt535V0tvbKGBYNuH4EF/33g/4T gXSzlipeXkvmuBnjhq9GVA+AP2V6lMQNQtShAvhrCYoHsHwLJyCT0UXAI3c6xuf3Xvws Q8nA== X-Gm-Message-State: AD7BkJLaw1XKRXXlOX4k2k3thOLubr9ACh3SEL+1FAss89DQnzsvsycrq35gS3sJftaSPDuJ X-Received: by 10.98.87.4 with SMTP id l4mr4853190pfb.15.1459589501982; Sat, 02 Apr 2016 02:31:41 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.92]) by smtp.gmail.com with ESMTPSA id i9sm25425804pfi.95.2016.04.02.02.31.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 02 Apr 2016 02:31:41 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, mark.rutland@arm.com, robh@kernel.org, grant.likely@secretlab.ca, linus.walleij@linaro.org, arnd.bergmann@linaro.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kong.kongxinwei@hisilicon.com, Guodong Xu Subject: [PATCH v2 12/16] arm64: dts: hi6220: add pinctrl for uarts and enable them Date: Sat, 2 Apr 2016 17:29:39 +0800 Message-Id: <1459589383-16914-13-git-send-email-guodong.xu@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459589383-16914-1-git-send-email-guodong.xu@linaro.org> References: <1459589383-16914-1-git-send-email-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 12 ++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e00e9ec..c4f560a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -50,6 +50,18 @@ i2c1: i2c@f7101000 { status = "ok"; }; + + uart1: uart@f7111000 { + status = "ok"; + }; + + uart2: uart@f7112000 { + status = "ok"; + }; + + uart3: uart@f7113000 { + status = "ok"; + }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index a7ca40b..6afd327 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -266,6 +266,8 @@ clocks = <&sys_ctrl HI6220_UART1_PCLK>, <&sys_ctrl HI6220_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; status = "disabled"; }; @@ -276,6 +278,8 @@ clocks = <&sys_ctrl HI6220_UART2_PCLK>, <&sys_ctrl HI6220_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; status = "disabled"; }; @@ -286,6 +290,9 @@ clocks = <&sys_ctrl HI6220_UART3_PCLK>, <&sys_ctrl HI6220_UART3_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; }; uart4: uart@f7114000 { @@ -295,6 +302,8 @@ clocks = <&sys_ctrl HI6220_UART4_PCLK>, <&sys_ctrl HI6220_UART4_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; status = "disabled"; };