From patchwork Tue Mar 22 20:23:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 64207 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2295799lbc; Tue, 22 Mar 2016 13:26:04 -0700 (PDT) X-Received: by 10.98.93.1 with SMTP id r1mr56356800pfb.57.1458678364129; Tue, 22 Mar 2016 13:26:04 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fu10si18406666pad.117.2016.03.22.13.26.03; Tue, 22 Mar 2016 13:26:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752724AbcCVUZ7 (ORCPT + 29 others); Tue, 22 Mar 2016 16:25:59 -0400 Received: from mail-io0-f180.google.com ([209.85.223.180]:33743 "EHLO mail-io0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752720AbcCVUX6 (ORCPT ); Tue, 22 Mar 2016 16:23:58 -0400 Received: by mail-io0-f180.google.com with SMTP id c63so75970817iof.0 for ; Tue, 22 Mar 2016 13:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rRBkZfuyUxLadmeVuQOAnNoV13AkaRP8ZSSckjzeMKM=; b=BeCmbjEUjOJE9UnVQVjau+DnxkXgUjabs+EtcEpa8cIIn3leXkfLZ/Icc4DiVFPdgv mSVJcs+G77qAar+MQa4tFfviecaK1K2PbHuM/xwLIunoFBdMHG/yYiZfUohoW5qUq+ap HJvDRa1a9fyaxPg1XDPM/WZC/TPlxFF7mue0A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rRBkZfuyUxLadmeVuQOAnNoV13AkaRP8ZSSckjzeMKM=; b=Lj19FH2fgzMpTnBdB2yCcEcNgFa4NyZZyaHZ3a1RUmWQ28EPntHd+aAyGlQJtlLHej XmeJHbozSp0HIAbSNBQ7b9uTGHrLGBbX8SAZyCfVpwab5jCjgfokWn7xy4BfA+Vx0SAu tcsmgTdAmk7pKaPr4M0YTOsLUTL/VBpxfipkJQlU0E1DaZkfGo8Gs/tMEGV0XdXSILC8 ofVj7VOvbMqPDeqlP/BjcTvHkWx/N2kcme0Ue3DbcFhUTUSDa5agm/013nwJ/c2Vk8YH 4WLlJCL4U93mk1MkQXJqdptcB6tlpOBFJtAH5Ovh5Pj3f+yrpFaLMyirnRoGPxmD4+0E ol9A== X-Gm-Message-State: AD7BkJJYpyuBm4XFCM/+0Sw0bzSsQhi4a61xj/ZSezXWixTjYlOuDEktf+Xk+N3DTcGeKTaq X-Received: by 10.107.18.70 with SMTP id a67mr41914658ioj.116.1458678237283; Tue, 22 Mar 2016 13:23:57 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xo2sm8092061igb.0.2016.03.22.13.23.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Mar 2016 13:23:56 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH 10/14] coresight: tmc: make sysFS and Perf mode mutually exclusive Date: Tue, 22 Mar 2016 14:23:18 -0600 Message-Id: <1458678202-3447-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> References: <1458678202-3447-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sysFS and Perf access methods can't be allowed to interfere with one another. As such introducing guards to access functions that prevents moving forward if a TMC is already being used. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 76 +++++++++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 77 ++++++++++++++++++++++--- 2 files changed, 139 insertions(+), 14 deletions(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a88c76d7f473..c533b4494969 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -106,7 +106,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev, u32 mode) { u32 val; bool allocated = false; @@ -127,6 +127,12 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) } val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* No need to continue if already operated from Perf */ + if (val == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + kfree(buf); + return -EBUSY; + } /* * In sysFS mode we can have multiple writers per sink. Since this * sink is already enabled no memory is needed and the HW need not be @@ -162,7 +168,7 @@ out: return 0; } -static void tmc_disable_etf_sink(struct coresight_device *csdev) +static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, u32 mode) { u32 val; unsigned long flags; @@ -171,16 +177,66 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETB/ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + tmc_etb_enable_hw(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return 0; +} + +static int tmc_enable_etf_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etf_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etf_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + +static void tmc_disable_etf_sink(struct coresight_device *csdev) +{ + u32 mode; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); return; } - val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); - /* Nothing to do, the TMC was already disabled */ - if (val == CS_MODE_DISABLED) + mode = local_xchg(&drvdata->mode, CS_MODE_DISABLED); + /* Nothing to do, the ETB/ETF was already disabled */ + if (mode == CS_MODE_DISABLED) goto out; + /* The engine has to be stopped in both sysFS and Perf mode */ tmc_etb_disable_hw(drvdata); - tmc_etb_dump_hw(drvdata); + + /* + * If we operated from sysFS, dump the trace data for retrieval + * via /dev/. From Perf trace data is handled via the Perf ring + * buffer. + */ + if (mode == CS_MODE_SYSFS) + tmc_etb_dump_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -253,7 +309,13 @@ int tmc_read_prepare_etf(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); - /* The TMC isn't enabled, so there is no need to disable it */ + /* Don't interfere if operated from Perf */ + if (local_read(&drvdata->mode) == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + /* The ETB/ETF isn't enabled, so there is no need to disable it */ if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETB/ETF is disabled already. If drvdata::buf is NULL diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 540d0b96a958..50a2e0a83714 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -82,7 +82,7 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode) { u32 val; bool allocated = false; @@ -109,6 +109,13 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) } val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* No need to continue if already operated from Perf */ + if (val == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr); + return -EBUSY; + } + /* * In sysFS mode we can have multiple writers per sink. Since this * sink is already enabled no memory is needed and the HW need not be @@ -143,7 +150,7 @@ out: return 0; } -static void tmc_disable_etr_sink(struct coresight_device *csdev) +static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, u32 mode) { u32 val; unsigned long flags; @@ -152,16 +159,66 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); + /* + * In Perf mode there can be only one writer per sink. There + * is also no need to continue if the ETR is already operated + * from sysFS. + */ + if (val != CS_MODE_DISABLED) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + tmc_etr_enable_hw(drvdata); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return 0; +} + +static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) +{ + switch (mode) { + case CS_MODE_SYSFS: + return tmc_enable_etr_sink_sysfs(csdev, mode); + case CS_MODE_PERF: + return tmc_enable_etr_sink_perf(csdev, mode); + } + + /* We shouldn't be here */ + return -EINVAL; +} + +static void tmc_disable_etr_sink(struct coresight_device *csdev) +{ + u32 mode; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); return; } - val = local_cmpxchg(&drvdata->mode, CS_MODE_SYSFS, CS_MODE_DISABLED); - /* Nothing to do, the TMC was already disabled */ - if (val == CS_MODE_DISABLED) + mode = local_xchg(&drvdata->mode, CS_MODE_DISABLED); + /* Nothing to do, the ETR was already disabled */ + if (mode == CS_MODE_DISABLED) goto out; + /* The engine has to be stopped in both sysFS and Perf mode */ tmc_etr_disable_hw(drvdata); - tmc_etr_dump_hw(drvdata); + + /* + * If we operated from sysFS, dump the trace data for retrieval + * via /dev/. From Perf trace data is handled via the Perf ring + * buffer. + */ + if (mode == CS_MODE_SYSFS) + tmc_etr_dump_hw(drvdata); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -184,7 +241,13 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); - /* The TMC isn't enabled, so there is no need to disable it */ + /* Don't interfere if operated from Perf */ + if (local_read(&drvdata->mode) == CS_MODE_PERF) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + + /* The ETR isn't enabled, so there is no need to disable it */ if (local_read(&drvdata->mode) == CS_MODE_DISABLED) { /* * The ETR is disabled already. If drvdata::buf is NULL