From patchwork Thu Mar 17 08:34:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun \(F\)" X-Patchwork-Id: 63947 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp327656lbc; Thu, 17 Mar 2016 01:35:00 -0700 (PDT) X-Received: by 10.66.102.70 with SMTP id fm6mr12870129pab.98.1458203700418; Thu, 17 Mar 2016 01:35:00 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q75si11025013pfq.207.2016.03.17.01.35.00; Thu, 17 Mar 2016 01:35:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933009AbcCQIev (ORCPT + 31 others); Thu, 17 Mar 2016 04:34:51 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:7958 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932935AbcCQIer (ORCPT ); Thu, 17 Mar 2016 04:34:47 -0400 Received: from 172.24.1.60 (EHLO szxeml434-hub.china.huawei.com) ([172.24.1.60]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DDR41787; Thu, 17 Mar 2016 16:34:16 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml434-hub.china.huawei.com (10.82.67.225) with Microsoft SMTP Server id 14.3.235.1; Thu, 17 Mar 2016 16:34:05 +0800 From: MaJun To: , , , , , , , , , , , , , , Subject: [PATCH v3 2/2] irqchip/mbigen:Change the mbigen driver based on the new mbigen node definition. Date: Thu, 17 Mar 2016 16:34:01 +0800 Message-ID: <1458203641-17172-3-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1458203641-17172-1-git-send-email-majun258@huawei.com> References: <1458203641-17172-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.56EA6C09.0009, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9e1fde47962185b0f2812b9cec1e7d9e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ma Jun In current mbigen driver, each mbigen device is initialized as a platform device. When these devices belong to same mbigen hardware module(chip), they use the same register definition in their device node and caused the problem of registers remapped repeatedly. Now, I try to initialize the mbigen module(chip) as a platform device and remap the register once to fix this problem. Signed-off-by: Ma Jun --- drivers/irqchip/irq-mbigen.c | 30 +++++++++++++++++++++--------- 1 files changed, 21 insertions(+), 9 deletions(-) -- 1.7.1 diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 4dd3eb8..4d413bc 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -242,6 +242,8 @@ static int mbigen_device_probe(struct platform_device *pdev) struct resource *res; struct irq_domain *domain; u32 num_pins; + struct platform_device *child_pdev; + struct device_node *np; mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); if (!mgn_chip) @@ -251,25 +253,35 @@ static int mbigen_device_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); mgn_chip->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mgn_chip->base)) return PTR_ERR(mgn_chip->base); - if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) { - dev_err(&pdev->dev, "No num-pins property\n"); - return -EINVAL; - } + for_each_child_of_node(pdev->dev.of_node, np) { + if (!of_property_read_bool(np, "interrupt-controller")) + continue; + + child_pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); + if (IS_ERR(child_pdev)) + return PTR_ERR(child_pdev); + + if (of_property_read_u32(child_pdev->dev.of_node, "num-pins", &num_pins) < 0) { + dev_err(&pdev->dev, "No num-pins property\n"); + return -EINVAL; + } - domain = platform_msi_create_device_domain(&pdev->dev, num_pins, + domain = platform_msi_create_device_domain(&child_pdev->dev, num_pins, mbigen_write_msg, &mbigen_domain_ops, mgn_chip); - if (!domain) - return -ENOMEM; + if (!domain) + return -ENOMEM; - platform_set_drvdata(pdev, mgn_chip); + dev_info(&child_pdev->dev, "Allocated %d MSIs\n", num_pins); + } - dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins); + platform_set_drvdata(pdev, mgn_chip); return 0; }