From patchwork Wed Mar 16 13:05:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 63927 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1309198lbc; Wed, 16 Mar 2016 06:06:10 -0700 (PDT) X-Received: by 10.98.67.195 with SMTP id l64mr5629006pfi.111.1458133570502; Wed, 16 Mar 2016 06:06:10 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id vp7si5092089pab.234.2016.03.16.06.06.10; Wed, 16 Mar 2016 06:06:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934952AbcCPNGI (ORCPT + 31 others); Wed, 16 Mar 2016 09:06:08 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:51471 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933997AbcCPNGG (ORCPT ); Wed, 16 Mar 2016 09:06:06 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2GD62Tg010190; Wed, 16 Mar 2016 08:06:02 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2GD61xu023466; Wed, 16 Mar 2016 08:06:02 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Wed, 16 Mar 2016 08:06:01 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2GD5whP012665; Wed, 16 Mar 2016 08:06:00 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 1/2] usb: dwc3: core: Introduce dwc3_device_reinit() Date: Wed, 16 Mar 2016 15:05:50 +0200 Message-ID: <1458133551-3071-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1458133551-3071-1-git-send-email-rogerq@ti.com> References: <1458133551-3071-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We will need this function for a workaround. The function issues a softreset only to the device controller and performs minimal re-initialization so that the device controller can be usable. As some code is similar to dwc3_core_init() take out common code into dwc3_get_gctl_quirks(). We add a new member (prtcap_mode) to struct dwc3 to keep track of the current mode in the PRTCAPDIR register. Signed-off-by: Roger Quadros --- drivers/usb/dwc3/core.c | 142 +++++++++++++++++++++++++++++++++--------------- drivers/usb/dwc3/core.h | 3 + 2 files changed, 102 insertions(+), 43 deletions(-) -- 2.5.0 diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 17fd8144..3b09494 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -58,6 +58,7 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |= DWC3_GCTL_PRTCAPDIR(mode); dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc->prtcap_mode = mode; } /** @@ -525,53 +526,16 @@ static int dwc3_phy_setup(struct dwc3 *dwc) } /** - * dwc3_core_init - Low-level initialization of DWC3 Core + * dwc3_get_gctl_quirks - Prepare GCTL register content with quirks + * and workarounds. * @dwc: Pointer to our controller context structure * - * Returns 0 on success otherwise negative errno. + * Returns 32-bit content that must be written into GCTL by caller. */ -static int dwc3_core_init(struct dwc3 *dwc) +static u32 dwc3_get_gctl_quirks(struct dwc3 *dwc) { - u32 hwparams4 = dwc->hwparams.hwparams4; - u32 reg; - int ret; - - reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); - /* This should read as U3 followed by revision number */ - if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { - /* Detected DWC_usb3 IP */ - dwc->revision = reg; - } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { - /* Detected DWC_usb31 IP */ - dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); - dwc->revision |= DWC3_REVISION_IS_DWC31; - } else { - dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); - ret = -ENODEV; - goto err0; - } - - /* - * Write Linux Version Code to our GUID register so it's easy to figure - * out which kernel version a bug was found. - */ - dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); - - /* Handle USB2.0-only core configuration */ - if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == - DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { - if (dwc->maximum_speed == USB_SPEED_SUPER) - dwc->maximum_speed = USB_SPEED_HIGH; - } - - /* issue device SoftReset too */ - ret = dwc3_soft_reset(dwc); - if (ret) - goto err0; - - ret = dwc3_core_soft_reset(dwc); - if (ret) - goto err0; + u32 reg; + u32 hwparams4 = dwc->hwparams.hwparams4; reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_SCALEDOWN_MASK; @@ -639,6 +603,59 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->revision < DWC3_REVISION_190A) reg |= DWC3_GCTL_U2RSTECN; + return reg; +} + +/** + * dwc3_core_init - Low-level initialization of DWC3 Core + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success otherwise negative errno. + */ +static int dwc3_core_init(struct dwc3 *dwc) +{ + u32 reg; + int ret; + + reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); + /* This should read as U3 followed by revision number */ + if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { + /* Detected DWC_usb3 IP */ + dwc->revision = reg; + } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { + /* Detected DWC_usb31 IP */ + dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); + dwc->revision |= DWC3_REVISION_IS_DWC31; + } else { + dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); + ret = -ENODEV; + goto err0; + } + + /* + * Write Linux Version Code to our GUID register so it's easy to figure + * out which kernel version a bug was found. + */ + dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); + + /* Handle USB2.0-only core configuration */ + if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == + DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { + if (dwc->maximum_speed == USB_SPEED_SUPER) + dwc->maximum_speed = USB_SPEED_HIGH; + } + + /* issue device SoftReset too */ + ret = dwc3_soft_reset(dwc); + if (ret) + goto err0; + + ret = dwc3_core_soft_reset(dwc); + if (ret) + goto err0; + + reg = dwc3_get_gctl_quirks(dwc); + dwc3_core_num_eps(dwc); dwc3_writel(dwc->regs, DWC3_GCTL, reg); @@ -666,6 +683,45 @@ err0: return ret; } +/** + * dwc3_device_reinit - Reset device controller and re-initialize. + * Can currently be called only if dwc->prtcap_mode == DWC3_GCTL_PRTCAP_DEVICE + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success otherwise negative errno. + */ +int dwc3_device_reinit(struct dwc3 *dwc) +{ + u32 reg; + int ret; + + if (dwc->prtcap_mode != DWC3_GCTL_PRTCAP_DEVICE) { + dev_err(dwc->dev, "%s can't be used for current_mode %d\n", + __func__, dwc->prtcap_mode); + return -EINVAL; + } + + dwc3_free_scratch_buffers(dwc); + + ret = dwc3_soft_reset(dwc); + if (ret) + return ret; + + reg = dwc3_get_gctl_quirks(dwc); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + dev_err(dwc->dev, "failed to setup event buffers\n"); + return ret; + } + + /* Set portcap. For now we support device only */ + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + + return ret; +} + static void dwc3_core_exit(struct dwc3 *dwc) { dwc3_free_scratch_buffers(dwc); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 6254b2f..2bea1ac 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -672,6 +672,7 @@ struct dwc3_scratchpad_array { * @maximum_speed: maximum speed requested (mainly for testing purposes) * @revision: revision register contents * @dr_mode: requested mode of operation + * @prtcap_mode: current mode of operation written to PRTCAPDIR * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY * @usb2_generic_phy: pointer to USB2 PHY @@ -774,6 +775,7 @@ struct dwc3 { size_t regs_size; enum usb_dr_mode dr_mode; + u32 prtcap_mode; /* used for suspend/resume */ u32 dcfg; @@ -1026,6 +1028,7 @@ struct dwc3_gadget_ep_cmd_params { /* prototypes */ void dwc3_set_mode(struct dwc3 *dwc, u32 mode); int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); +int dwc3_device_reinit(struct dwc3 *dwc); /* check whether we are on the DWC_usb31 core */ static inline bool dwc3_is_usb31(struct dwc3 *dwc)