From patchwork Mon Mar 14 06:45:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun \(F\)" X-Patchwork-Id: 63794 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2311574lbc; Sun, 13 Mar 2016 23:46:15 -0700 (PDT) X-Received: by 10.66.102.70 with SMTP id fm6mr35209105pab.98.1457937974883; Sun, 13 Mar 2016 23:46:14 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id uj10si1662845pac.79.2016.03.13.23.46.14; Sun, 13 Mar 2016 23:46:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933525AbcCNGqB (ORCPT + 31 others); Mon, 14 Mar 2016 02:46:01 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:37709 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932252AbcCNGpj (ORCPT ); Mon, 14 Mar 2016 02:45:39 -0400 Received: from 172.24.1.60 (EHLO szxeml422-hub.china.huawei.com) ([172.24.1.60]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BXY20620; Mon, 14 Mar 2016 14:45:19 +0800 (CST) Received: from localhost (10.177.235.245) by szxeml422-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.235.1; Mon, 14 Mar 2016 14:45:09 +0800 From: MaJun To: , , , , , , , , , , , , , , Subject: [PATCH v2 1/2] Irq/mbigen:Change the mbigen node definition in dt binding file Date: Mon, 14 Mar 2016 14:45:06 +0800 Message-ID: <1457937907-14008-2-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1457937907-14008-1-git-send-email-majun258@huawei.com> References: <1457937907-14008-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.56E65E00.0060, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5350c99929fc840fb2a432bc08dac18e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ma Jun For mbigen module, there is a special case that more than one mbigen device nodes use the same reg definition in DTS when these devices exist in the same mbigen hardware module. To fix the mbigen IO remap problem, the mbigen node definition and structure are changed based on Mark Rutland's suggestion. Signed-off-by: Ma Jun --- .../interrupt-controller/hisilicon,mbigen-v2.txt | 22 +++++++++++++++---- 1 files changed, 17 insertions(+), 5 deletions(-) -- 1.7.1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt index 720f7c9..3b2f4c4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt @@ -21,6 +21,8 @@ Mbigen main node required properties: - reg: Specifies the base physical address and size of the Mbigen registers. +Mbigen sub node required properties: +------------------------------------------ - interrupt controller: Identifies the node as an interrupt controller - msi-parent: Specifies the MSI controller this mbigen use. @@ -45,13 +47,23 @@ Mbigen main node required properties: Examples: - mbigen_device_gmac:intc { + mbigen_chip_dsa { compatible = "hisilicon,mbigen-v2"; reg = <0x0 0xc0080000 0x0 0x10000>; - interrupt-controller; - msi-parent = <&its_dsa 0x40b1c>; - num-pins = <9>; - #interrupt-cells = <2>; + + mbigen_gmac:intc_gmac { + interrupt-controller; + msi-parent = <&its_dsa 0x40b1c>; + num-pins = <9>; + #interrupt-cells = <2>; + }; + + mbigen_i2c:intc_i2c { + interrupt-controller; + msi-parent = <&its_dsa 0x40b0e>; + num-pins = <2>; + #interrupt-cells = <2>; + }; }; Devices connect to mbigen required properties: