From patchwork Tue Mar 1 13:44:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 63306 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1834674lbc; Tue, 1 Mar 2016 05:45:22 -0800 (PST) X-Received: by 10.66.145.68 with SMTP id ss4mr30233093pab.79.1456839922277; Tue, 01 Mar 2016 05:45:22 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fg8si11575349pad.227.2016.03.01.05.45.21; Tue, 01 Mar 2016 05:45:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754096AbcCANpH (ORCPT + 30 others); Tue, 1 Mar 2016 08:45:07 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:58545 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754044AbcCANpA (ORCPT ); Tue, 1 Mar 2016 08:45:00 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u21DivAm026046; Tue, 1 Mar 2016 07:44:57 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u21DivWJ020515; Tue, 1 Mar 2016 07:44:57 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Tue, 1 Mar 2016 07:44:56 -0600 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u21Dios9010748; Tue, 1 Mar 2016 07:44:55 -0600 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 2/2] ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND Date: Tue, 1 Mar 2016 15:44:48 +0200 Message-ID: <1456839888-6244-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456839888-6244-1-git-send-email-rogerq@ti.com> References: <1456839888-6244-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] dm814x TRM: SPRUGZ8F: 11.2.4.12.2 NAND Device-Ready Pin Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dm8148-evm.dts | 3 --- arch/arm/boot/dts/dra62x-j5eco-evm.dts | 3 --- 2 files changed, 6 deletions(-) -- 2.5.0 diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index be56c8f..cbc17b0 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -65,12 +65,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; partition@0 { diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index b0c8144..f820573 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -65,12 +65,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; partition@0 {