From patchwork Mon Feb 29 18:54:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 63243 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1414530lbc; Mon, 29 Feb 2016 10:55:38 -0800 (PST) X-Received: by 10.98.14.2 with SMTP id w2mr5976912pfi.35.1456772137812; Mon, 29 Feb 2016 10:55:37 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w2si12378897pfa.51.2016.02.29.10.55.37; Mon, 29 Feb 2016 10:55:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753931AbcB2Sze (ORCPT + 30 others); Mon, 29 Feb 2016 13:55:34 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:36335 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753726AbcB2Syx (ORCPT ); Mon, 29 Feb 2016 13:54:53 -0500 Received: by mail-pa0-f54.google.com with SMTP id yy13so96383090pab.3 for ; Mon, 29 Feb 2016 10:54:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p+3omOme+vCNJvo3EhQuiqQ0MkKwCxm8GZhYnBV8HZQ=; b=SsDU8iprrAcAhzeQGSziwUnB9l6ABlK+DdEA86/AWc4iEu2py2b5hDgB2w7tnEKHu4 NgCEyescW5fd9vpRWkg5a5mt+NJzv+nerGACvWHwlUnhIwXAXEL5NMvqLcg9NYZYrvgW C4yMDcvm5s9INXWXnOlpD4LQIRvP5sL7BXsfM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p+3omOme+vCNJvo3EhQuiqQ0MkKwCxm8GZhYnBV8HZQ=; b=CKaSc4G42iCeB+yz35CBH3ckC9btqf2hwl3yO4BooMPchG8G/DzWYJF+xBetMp9Rr0 zDvHtXBmP+Ll4UhVELfRAmrdkh84fWs0MGtkGzHthcsuHF/MFtlmpNneK6qPi9BgAhKS /jf/IkxiVDER7O6yUH04shhdwU8KhDHQhi8MpmB/+oj8LluFb5bktmbRLoVL7Wg8V3OI mVpcXrgIhUQIOmpI+0jJEH/7uP878B8yER/GGHzg7LzI1T8hLLKkQJx9h21tB7Qi55ea NqHelrHR7wjk12qqfGRBIoKfKCznziAy21pR2VJUZkPzTT1AOIyGHVowi+cXbX31XStO 1trA== X-Gm-Message-State: AD7BkJJIiCHmd7uRCBiWL4SVgRyU/i/3y807UylPjhWmKHuEMvuoIc0JtZnN6JGN1D9KKhBw X-Received: by 10.66.233.131 with SMTP id tw3mr24491211pac.89.1456772092458; Mon, 29 Feb 2016 10:54:52 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id l24sm39783355pfb.73.2016.02.29.10.54.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 Feb 2016 10:54:51 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com Subject: [PATCH 7/8] coresight: etm4x: implementing user/kernel mode tracing Date: Mon, 29 Feb 2016 11:54:26 -0700 Message-Id: <1456772067-18085-8-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> References: <1456772067-18085-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 3 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 35 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 5 +++- 3 files changed, 42 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index a996db7ef2fc..0e80ec668402 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -440,6 +440,9 @@ static ssize_t mode_store(struct device *dev, else config->vinst_ctrl &= ~BIT(11); + if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) + etm4_config_trace_mode(config); + spin_unlock(&drvdata->spinlock); return size; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 738acee18967..743c34b92a80 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -567,6 +567,41 @@ static void etm4_set_default(struct etmv4_config *config) config->vissctlr = 0x0; } +void etm4_config_trace_mode(struct etmv4_config *config) +{ + u32 addr_acc, mode; + + mode = config->mode; + mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); + + /* excluding kernel AND user space doesn't make sense */ + WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); + + /* nothing to do if neither flags are set */ + if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) + return; + + addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP]; + /* clear default config */ + addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS); + + /* + * EXLEVEL_NS, bits[15:12] + * The Exception levels are: + * Bit[12] Exception level 0 - Application + * Bit[13] Exception level 1 - OS + * Bit[14] Exception level 2 - Hypervisor + * Bit[15] Never implemented + */ + if (mode & ETM_MODE_EXCL_KERN) + addr_acc |= ETM_EXLEVEL_NS_OS; + else + addr_acc |= ETM_EXLEVEL_NS_APP; + + config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc; + config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc; +} + static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index f7748ae63451..a291d4cc8bd8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -176,7 +176,9 @@ #define ETM_MODE_TRACE_RESET BIT(25) #define ETM_MODE_TRACE_ERR BIT(26) #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) -#define ETMv4_MODE_ALL 0xFFFFFFF +#define ETMv4_MODE_ALL (GENMASK(27, 0) | \ + ETM_MODE_EXCL_KERN | \ + ETM_MODE_EXCL_USER) #define TRCSTATR_IDLE_BIT 0 #define ETM_DEFAULT_ADDR_COMP 0 @@ -414,4 +416,5 @@ enum etm_addr_type { }; extern const struct attribute_group *coresight_etmv4_groups[]; +void etm4_config_trace_mode(struct etmv4_config *config); #endif