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redhat.com; dmarc=none action=none header.from=amd.com; Received: from localhost.localdomain (124.121.8.20) by BLUPR12MB0434.namprd12.prod.outlook.com (10.162.92.14) with Microsoft SMTP Server (TLS) id 15.1.415.20; Mon, 29 Feb 2016 04:23:49 +0000 From: Suravee Suthikulpanit To: , , CC: , , , , Suravee Suthikulpanit , Suravee Suthikulpanit Subject: [PATCH v2] perf/x86/amd: Adding support for new IOMMU performance event Date: Sun, 28 Feb 2016 22:23:29 -0600 Message-ID: <1456719809-20906-1-git-send-email-Suravee.Suthikulpanit@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [124.121.8.20] X-ClientProxiedBy: SIXPR04CA0045.apcprd04.prod.outlook.com (25.162.171.35) To BLUPR12MB0434.namprd12.prod.outlook.com (25.162.92.14) X-MS-Office365-Filtering-Correlation-Id: a59893b3-dd93-4404-7f40-08d340c02444 X-Microsoft-Exchange-Diagnostics: 1; BLUPR12MB0434; 2:QqEuZzq0iWR1kpkJJFI1z0JhzvZwGrpdKbD2sAqbLUoPeX4sXtWe6B84udntcfF9CR/o+J6hHHn7E8LOmwPVmE7BlDZ2eS2meKWbz8KkdzLrQJZ2CezW4Ak/gcxJhmHsP4hPtZLZa/YjJLY7ct/UUuNTmUbfftNMVilQgfBZW1GOTrG2OzbnL/OZIKdiWHaf; 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BLUPR12MB0434; 5:dQyqm8knCDaIVcjq5Hz4sskdsWs5bpdSixDvjnLCHWN3Mgf7lWxbhB7SSm3QDrtGTF1+qBC0q+S+lme/7dV9A/ccE+1RidoLaDuTbVgiKNorznKV7yAo1E6lrtkhx+XoHeeASgdvQSGYczaih7OwPQ==; 24:eFqomtfNX44Kl8ox870eOPb3QCePl3sk8MPlIcQcDV2vLRlEuk969nr401VAmEXfp8Clxv13al5/Xu5EDN+RHGrtc9D5cROYJ0rdJkINSFs=; 20:NWAhA4iWsXFpivx4pnzACbH9fD8WU6oDViQN6C+Yxo8nPydcdUFzyGLt844lQhmlg/PVbwUf/vKHv+bs2drSzKuG546D+ahPwcYouSIq0cyRwKa4p1jA2VD1jNGdIB10iTpjb4p5EAlWxWsAh9ush8vFiT6nGPwQdjmuHhK2KyjmQ3vGiFDpHL8zgBe8/eTqWRKIvJukDuX8NI33zRYzfHIrAVTBML21NJBpkBPRNWM2bxibvitRVRnCh8cDbmCH X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Feb 2016 04:23:49.2611 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR12MB0434 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds new IOMMU performance event based on the information in table 74 of the AMD I/O Virtualization Technology (IOMMU) Specification (Document Id: 4882, Rev 2.62, Feb 2015) Link: http://support.amd.com/TechDocs/48882_IOMMU.pdf Reviewed-by: Joerg Roedel Acked-by: Joerg Roedel Signed-off-by: Suravee Suthikulpanit --- Hi Ingo/Peter, I have re-based the patch from tips, and re-send this as V2. If there is no other concern, would you please accept this patch when you get a chance. FYI, here is the link to V1 (https://lkml.org/lkml/2015/12/11/891). Thanks, Suravee arch/x86/events/amd/iommu.c | 5 +++++ 1 file changed, 5 insertions(+) -- 1.9.1 diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 635e5eb..40625ca 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -118,6 +118,11 @@ static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = { AMD_IOMMU_EVENT_DESC(cmd_processed, "csource=0x11"), AMD_IOMMU_EVENT_DESC(cmd_processed_inv, "csource=0x12"), AMD_IOMMU_EVENT_DESC(tlb_inv, "csource=0x13"), + AMD_IOMMU_EVENT_DESC(ign_rd_wr_mmio_1ff8h, "csource=0x14"), + AMD_IOMMU_EVENT_DESC(vapic_int_non_guest, "csource=0x15"), + AMD_IOMMU_EVENT_DESC(vapic_int_guest, "csource=0x16"), + AMD_IOMMU_EVENT_DESC(smi_recv, "csource=0x17"), + AMD_IOMMU_EVENT_DESC(smi_blk, "csource=0x18"), { /* end: all zeroes */ }, };