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[209.132.180.67]) by mx.google.com with ESMTP id c8si8685789pat.62.2016.02.24.17.45.17; Wed, 24 Feb 2016 17:45:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@gmail.com; dmarc=pass (p=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758879AbcBYBpO (ORCPT + 30 others); Wed, 24 Feb 2016 20:45:14 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:35992 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751448AbcBYBpL (ORCPT ); Wed, 24 Feb 2016 20:45:11 -0500 Received: by mail-pa0-f41.google.com with SMTP id yy13so22627259pab.3 for ; Wed, 24 Feb 2016 17:45:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=IOCb+ZVH39QcPbU7NMOZLJLQhxcJG2QQHKEgSfKgrM0=; b=w+9aqgewQ5hh3wNeE2jNKnXrCI+UN8L7QzQDuFXT8R2Ozt+iv/HRhEGvjGT6uN9H2l oQ1ymeyWf9QYc5iXwMfMqUeF8Y0tAOACh9r/kqI7f0O9e84OCsMI2TvXHfud7OaNyCF2 ESD+FbLvV9O6HDSI7S4jnAYB94XqzI0Fq3nWHVLU1wG83hdS9B+2FmxROTAB7zzFRSWU Cj46rXNaK/cPmoSglxSKac7M9ut8OAEfG4nyrHfsDqE7fNPT6xTvssKakr34lxCTDuRw ErnGTBh9UpzDB1WwbmVO/xY4K0tSC6cILXU2J6wm9+u0TvzEfUNRQmosciB4HmhQSzDM Fh8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=IOCb+ZVH39QcPbU7NMOZLJLQhxcJG2QQHKEgSfKgrM0=; b=HWiKFjNvDSJdAhnfWAV78Wz5cIdZALgADXboEx44/qxUivISR6/vIPAWH1I+uj1YoC SkrUkom8yqsfSXi0p/VlCGsFt6Nu+aIg8ts4y1Rvd3z8GDoHyVlBJ2OEJCAK3FgPEyGp QwhJvulpxdaSD6n/xQ2xYkCZ1bERJEqB1PTRtqAVRfKg2StoCMMjEi2qk0taLFZ6lOuB ExucXMdLCrpVoMXM5cLGthfprGgjwL/GpLpjial9r4ncVpwjoCFwtAfvk/i27FmF2L4W bOQUv6yNWxNkTh7q5RbJGNEle3AMzxsjUDatG/Kk+5XfuYqndtHkZ7kv+7q2bR6iheyz ZB+w== X-Gm-Message-State: AG10YORrMywqBqLn0qityPoxBdduBNVfyZOKbP4mLhDchfo0iMKqSb8tthkmgeRBbp5GDw== X-Received: by 10.66.253.193 with SMTP id ac1mr59403398pad.121.1456364711244; Wed, 24 Feb 2016 17:45:11 -0800 (PST) Received: from dl.caveonetworks.com ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id xa9sm7718105pab.44.2016.02.24.17.45.08 (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 24 Feb 2016 17:45:09 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id u1P1j8Yc025117; Wed, 24 Feb 2016 17:45:08 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id u1P1j7aQ025116; Wed, 24 Feb 2016 17:45:07 -0800 From: David Daney To: Will Deacon , linux-arm-kernel@lists.infradead.org, Mark Rutland , Catalin Marinas , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Andrew Pinski , David Daney Subject: [PATCH v4] arm64: Add workaround for Cavium erratum 27456 Date: Wed, 24 Feb 2016 17:44:57 -0800 Message-Id: <1456364697-25083-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which invalidates the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski Signed-off-by: David Daney Reviewed-by: Will Deacon --- v4: - Add Reviewed-by - Improve wording of changlog and Kconfig help - Updated capability constant hoping that it eases merging with KVM patches Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpufeature.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 9 +++++++++ arch/arm64/mm/proc.S | 12 ++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) -- 1.8.3.1 diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71dd..ba4b6ac 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b646091..97cd2b9 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -435,6 +435,17 @@ config CAVIUM_ERRATUM_23154 If unsure, say Y. +config CAVIUM_ERRATUM_27456 + bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" + default y + help + On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI + instructions may cause the icache to become corrupted if it + contains data for a non-current ASID. The fix is to + invalidate the icache when changing the mm context. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 37a53fc..727e594 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -33,8 +33,9 @@ #define ARM64_HAS_NO_HW_PREFETCH 8 #define ARM64_HAS_UAO 9 #define ARM64_ALT_PAN_NOT_UAO 10 +#define ARM64_WORKAROUND_CAVIUM_27456 12 -#define ARM64_NCAPS 11 +#define ARM64_NCAPS 13 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index e6bc988..06afd04 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -88,6 +88,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_27456 + { + /* Cavium ThunderX, T88 pass 1.x - 2.1 */ + .desc = "Cavium erratum 27456", + .capability = ARM64_WORKAROUND_CAVIUM_27456, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 1), + }, +#endif { } }; diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 0c19534..543f519 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "proc-macros.S" @@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb + ret +alternative_endif ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"