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[209.132.180.67]) by mx.google.com with ESMTP id wq13si476609pac.86.2016.02.23.16.09.05; Tue, 23 Feb 2016 16:09:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@gmail.com; dmarc=pass (p=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752970AbcBXAJB (ORCPT + 30 others); Tue, 23 Feb 2016 19:09:01 -0500 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34137 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752240AbcBXAJA (ORCPT ); Tue, 23 Feb 2016 19:09:00 -0500 Received: by mail-pf0-f176.google.com with SMTP id x65so1547189pfb.1 for ; Tue, 23 Feb 2016 16:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=frXlC+wSZVBf6/NIrEc2AfQeZKfWkL4U2XvQLcg+kg8=; b=BFcHrJVUQ3o2MqWJVDPmoiSpG+iqVyaWuYpmEgAFB+ZkkYxpNDsPSB94YDx2zsPq8a A6rk57NpgPcwEazxLn3W+x9zailKBx3YRFkuUzMdEBwN9Y1uJv8XGniJ/9pYVWu11GB/ Zf6lPXILziWMOmDGes5NXQzrBKY7UkrVRUhlHIPjtM7FkR7YZfW94SRbaFXnztO85ZLZ G9mr9oCLffJHxuwCZf+1yO4UrypfX5Kn9amr+FJlbvGDYD1KespF/czWVamnEkUISlz1 cET0SlHgJmotvZjEWaflZhyWdBoy6/NGhQxI0Jo3n3ln/nKALCZa4qIKatHLCWE4DXej ClIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=frXlC+wSZVBf6/NIrEc2AfQeZKfWkL4U2XvQLcg+kg8=; b=ZgHfyTI13xaQ7bPKZ0mgzITXo5k3JfHSfJYWszpmdQnd4j3c2JDXLz3+2bj/IPRiCK BqOfMWnc15HVIhYnLb1jqlOBCNd0+i1q/snsxbHkQJ79ojQbZ/0pGO7eIc9q1EG4IXUt ERXi+JyYhDKmU3UOzyj4MjeYaIDeYPB081jMc6ONLqBsuK1sHHyWVr31kt+99MEKoMi9 G8K4mcN5wwJWlrXk2AYGHhgBBrjruC84BPLPdevDe+mgNcrHOkNfx4hEnW5TvcbaANsr Y4/DRXefzU+x1cL+DBENs3Xa754Y+rX7B2/HHvNYqcBV7twfKGxWtezgFQaoQTx2t60F Y3WA== X-Gm-Message-State: AG10YOTFE4TqYIkTJ35VxPJ4LL3Zc+ZbWrWm1pSC8N+9lF7mTX5MQFuzldi+P/jUtaxIHg== X-Received: by 10.98.9.129 with SMTP id 1mr50649737pfj.163.1456272539400; Tue, 23 Feb 2016 16:08:59 -0800 (PST) Received: from dl.caveonetworks.com ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id 79sm196474pfq.65.2016.02.23.16.08.57 (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 23 Feb 2016 16:08:57 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id u1O08uGB021725; Tue, 23 Feb 2016 16:08:56 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id u1O08tNB021724; Tue, 23 Feb 2016 16:08:55 -0800 From: David Daney To: Will Deacon , linux-arm-kernel@lists.infradead.org, Mark Rutland , Catalin Marinas , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Andrew Pinski , David Daney Subject: [PATCH v3] arm64: Add workaround for Cavium erratum 27456 Date: Tue, 23 Feb 2016 16:08:54 -0800 Message-Id: <1456272534-21692-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which flushes the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski Signed-off-by: David Daney --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpufeature.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 9 +++++++++ arch/arm64/mm/proc.S | 12 ++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) -- 1.8.3.1 Reviewed-by: Will Deacon diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71dd..ba4b6ac 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8cc6228..39f2203 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -432,6 +432,17 @@ config CAVIUM_ERRATUM_23154 If unsure, say Y. +config CAVIUM_ERRATUM_27456 + bool "Cavium erratum 27456: Broadcast TLBI instructions may cause the icache corruption" + default y + help + On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI + instructions may cause the icache to become corrupted if it + contains data for a non-current ASID. The fix is to flush + the icache when changing the mm context. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8f271b8..8136afc 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -30,8 +30,9 @@ #define ARM64_HAS_LSE_ATOMICS 5 #define ARM64_WORKAROUND_CAVIUM_23154 6 #define ARM64_WORKAROUND_834220 7 +#define ARM64_WORKAROUND_CAVIUM_27456 8 -#define ARM64_NCAPS 8 +#define ARM64_NCAPS 9 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index feb6b4e..a3e846a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -100,6 +100,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_27456 + { + /* Cavium ThunderX, T88 pass 1.x - 2.1 */ + .desc = "Cavium erratum 27456", + .capability = ARM64_WORKAROUND_CAVIUM_27456, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 1), + }, +#endif { } }; diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c164d2c..0f3be00 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "proc-macros.S" @@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb + ret +alternative_endif ENDPROC(cpu_do_switch_mm) /*