From patchwork Tue Feb 23 16:37:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 62734 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp1927301lbl; Tue, 23 Feb 2016 08:38:12 -0800 (PST) X-Received: by 10.66.244.233 with SMTP id xj9mr27397946pac.19.1456245492089; Tue, 23 Feb 2016 08:38:12 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t75si48271181pfa.9.2016.02.23.08.38.11; Tue, 23 Feb 2016 08:38:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754383AbcBWQiE (ORCPT + 30 others); Tue, 23 Feb 2016 11:38:04 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:57710 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754296AbcBWQiA (ORCPT ); Tue, 23 Feb 2016 11:38:00 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1NGbueJ032108; Tue, 23 Feb 2016 10:37:56 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1NGbuFn016815; Tue, 23 Feb 2016 10:37:56 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Tue, 23 Feb 2016 10:37:56 -0600 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1NGbQcX016993; Tue, 23 Feb 2016 10:37:53 -0600 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v7 8/9] ARM: dts: dm8168-evm: ARM: dts: Disable wait pin monitoring for NAND Date: Tue, 23 Feb 2016 18:37:24 +0200 Message-ID: <1456245445-31824-9-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456245445-31824-1-git-send-email-rogerq@ti.com> References: <1456245445-31824-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] dm816x TRM: SPRUGX8C: 9.2.4.12.2 NAND Device-Ready Pin Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dm8168-evm.dts | 3 --- 1 file changed, 3 deletions(-) -- 2.5.0 diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 0cb1003..f50348b 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -111,12 +111,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; partition@0 {