From patchwork Tue Feb 9 21:16:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 61595 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp2280283lbl; Tue, 9 Feb 2016 13:16:51 -0800 (PST) X-Received: by 10.98.17.92 with SMTP id z89mr53906714pfi.16.1455052611695; Tue, 09 Feb 2016 13:16:51 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ur7si56213660pac.223.2016.02.09.13.16.51; Tue, 09 Feb 2016 13:16:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@gmail.com; dmarc=pass (p=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932979AbcBIVQt (ORCPT + 30 others); Tue, 9 Feb 2016 16:16:49 -0500 Received: from mail-pa0-f65.google.com ([209.85.220.65]:32818 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932434AbcBIVQr (ORCPT ); Tue, 9 Feb 2016 16:16:47 -0500 Received: by mail-pa0-f65.google.com with SMTP id y7so65965paa.0 for ; Tue, 09 Feb 2016 13:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=fvsru9/WSF7se62y4U1ZnC/6nx66G4so39tQ9PmQOhw=; b=zmNg4opCwkqWWoVeK82lO6P2QhdkNz2z0qSgWCQ9t3cP9+y7iA7Mj3onZnd5P/0M8Y BfYY8ccM7gG7JmNZvvvCnMZxUL6ATQSTvKObfAqIGX67iB1xLSqJBpTzZaQk5urzwKOx WzHrsuhjMfoYT/PCoDJs1Ta3xY2YGY4xITmzv2hffzp/ATyACyg4afL+9OYpZEdanoqZ 353sowd82My8qfCqJJirBgBDKh8OpM4XIaa0wAe8w2QMWCeHIRGSv2LEoYTyxD0IWMfm 9iPrWuDMNhmvPeZc/BtSRlrPspIjILKCvL4BGuQcSsilxH4hRb9vpDD+3JuC9bsGd8Bg bMig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fvsru9/WSF7se62y4U1ZnC/6nx66G4so39tQ9PmQOhw=; b=ayyC3XFM9WRv8pBowxsKqde8bV/lye0RUxlijq5oMur7iCxKOkheYKjSqoisQds5Mg Ff1pCsddq80uFFIEdCiHmZ/nP4rui+94o12moc2BUIPkyieCloG8v+Wa/v6aASe03wxw BZU6B7NshqLSloAFlp6Fcr6B6WiLM5X8jCTcjOCn+yOXzlksbHQRQ94eaT8hykrcnqvZ Jp0+fG4gazc1DzlVWxH6eBQm6XDiPsQ9I0Po037QcEX5Ia7xm/C/ExSlvMt51Y/SXsB9 Hltaq5LQEZNK69xS4hjBPn4Ldonp0GoUbUoPLeGORZoqIx1f9WIKF3IboIvIZbSi5KEj 4+Iw== X-Gm-Message-State: AG10YOR4eLRfEQPgQB6TYuK1rJuh7H4tbzKeF9iiCxqgOY4vy8waYtHIIVf6QZ5CwY05PQ== X-Received: by 10.66.141.165 with SMTP id rp5mr53719520pab.56.1455052607174; Tue, 09 Feb 2016 13:16:47 -0800 (PST) Received: from dl.caveonetworks.com ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id h66sm52587060pfd.91.2016.02.09.13.16.45 (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 09 Feb 2016 13:16:45 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id u19LGi1t011452; Tue, 9 Feb 2016 13:16:44 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id u19LGerR011450; Tue, 9 Feb 2016 13:16:40 -0800 From: David Daney To: Will Deacon , linux-arm-kernel@lists.infradead.org, Mark Rutland , Catalin Marinas , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Andrew Pinski , David Daney Subject: [PATCH v2] arm64: Add workaround for Cavium erratum 27456 Date: Tue, 9 Feb 2016 13:16:39 -0800 Message-Id: <1455052599-11418-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This patch implements the workaround (which flushes the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski Signed-off-by: David Daney --- Changes from v1: Add entry to silicon-errata.txt Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpufeature.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 9 +++++++++ arch/arm64/mm/proc.S | 12 ++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) -- 1.8.3.1 diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71dd..ba4b6ac 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8cc6228..a969970 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -432,6 +432,17 @@ config CAVIUM_ERRATUM_23154 If unsure, say Y. +config CAVIUM_ERRATUM_27456 + bool "Cavium erratum 27456: Broadcast TLBI instructions may cause the icache to become invalid" + default y + help + On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI + instructions may cause the icache to become invalid if it + contains data for a non-current ASID. The fix is to flush + the icache when changing the mm context. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8f271b8..8136afc 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -30,8 +30,9 @@ #define ARM64_HAS_LSE_ATOMICS 5 #define ARM64_WORKAROUND_CAVIUM_23154 6 #define ARM64_WORKAROUND_834220 7 +#define ARM64_WORKAROUND_CAVIUM_27456 8 -#define ARM64_NCAPS 8 +#define ARM64_NCAPS 9 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index feb6b4e..a3e846a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -100,6 +100,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_27456 + { + /* Cavium ThunderX, T88 pass 1.x - 2.1 */ + .desc = "Cavium erratum 27456", + .capability = ARM64_WORKAROUND_CAVIUM_27456, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 1), + }, +#endif { } }; diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c164d2c..0f3be00 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "proc-macros.S" @@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb + ret +alternative_endif ENDPROC(cpu_do_switch_mm) /*