From patchwork Thu Feb 4 11:37:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 61175 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp397363lbl; Thu, 4 Feb 2016 03:24:30 -0800 (PST) X-Received: by 10.98.76.19 with SMTP id z19mr10049125pfa.78.1454585070331; Thu, 04 Feb 2016 03:24:30 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id lr5si16132331pab.147.2016.02.04.03.24.29; Thu, 04 Feb 2016 03:24:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753658AbcBDLY2 (ORCPT + 30 others); Thu, 4 Feb 2016 06:24:28 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:16779 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751411AbcBDLYW (ORCPT ); Thu, 4 Feb 2016 06:24:22 -0500 Received: from 172.24.1.47 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.47]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DED57510; Thu, 04 Feb 2016 19:22:55 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 4 Feb 2016 19:22:47 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH 4/4] PCI/ACPI: hisi: Add ACPI support for HiSilicon SoCs Host Controllers Date: Thu, 4 Feb 2016 19:37:40 +0800 Message-ID: <1454585860-60709-5-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> References: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0206.56B33491.0179, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a139ed8b376fe2844d21ed0ae9539c94 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni This patch adds specific quirks for PCI config space accessors, it uses _HID to decide whether to hook pci_ops or not. Signed-off-by: Dongdong Liu Signed-off-by: Gabriele Paoloni --- MAINTAINERS | 1 + drivers/pci/host/Kconfig | 9 +++ drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-hisi-acpi.c | 147 ++++++++++++++++++++++++++++++++++++++ drivers/pci/host/pcie-hisi.c | 2 - drivers/pci/host/pcie-hisi.h | 6 ++ 6 files changed, 164 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/host/pcie-hisi-acpi.c -- 1.9.1 diff --git a/MAINTAINERS b/MAINTAINERS index 8d6ec25..d35c300 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8250,6 +8250,7 @@ F: Documentation/devicetree/bindings/pci/hisilicon-pcie.txt F: drivers/pci/host/pcie-hisi.h F: drivers/pci/host/pcie-hisi.c F: drivers/pci/host/pcie-hisi-common.c +F: drivers/pci/host/pcie-hisi-acpi.c PCMCIA SUBSYSTEM P: Linux PCMCIA Team diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 4d385d6..7a6b80d 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -174,4 +174,13 @@ config PCI_HISI Say Y here if you want PCIe controller support on HiSilicon Hip05 and Hip06 SoCs +config PCI_HISI_ACPI + bool "ACPI PCI HiSilicon SoC HIP05 PCIe controller" + depends on ACPI + select ACPI_PCI_HOST_GENERIC + select PCIE_DW + help + Say Y here if you want ACPI PCIe controller support on + HiSilicon Hip05 and Hip06 SoCs + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 6248320..ff010b6 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o obj-$(CONFIG_PCI_HISI) += pcie-hisi.o pcie-hisi-common.o +obj-$(CONFIG_PCI_HISI_ACPI) += pcie-hisi-acpi.o pcie-hisi-common.o diff --git a/drivers/pci/host/pcie-hisi-acpi.c b/drivers/pci/host/pcie-hisi-acpi.c new file mode 100644 index 0000000..1bca4f1 --- /dev/null +++ b/drivers/pci/host/pcie-hisi-acpi.c @@ -0,0 +1,147 @@ +/* + * PCIe host controller driver for HiSilicon HipXX SoCs + * + * Copyright (C) 2016 HiSilicon Co., Ltd. http://www.hisilicon.com + * + * Author: Dongdong Liu + * Gabriele Paoloni + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-hisi.h" + +#define GET_PCIE_LINK_STATUS 0x0 + +/* uuid 6d30f553-836c-408e-b6ad-45bccc957949 */ +const u8 hisi_pcie_acpi_dsm_uuid[] = { + 0x53, 0xf5, 0x30, 0x6d, 0x6c, 0x83, 0x8e, 0x40, + 0xb6, 0xad, 0x45, 0xbc, 0xcc, 0x95, 0x79, 0x49 +}; + +static const struct acpi_device_id hisi_pcie_ids[] = { + {"HISI0080", 0}, + {"", 0}, +}; + +static int hisi_pcie_get_addr(struct acpi_pci_root *root, const char *name, + void __iomem **addr) +{ + struct acpi_device *device; + u64 base; + u64 size; + u32 buf[4]; + int ret; + + device = root->device; + ret = fwnode_property_read_u32_array(&device->fwnode, name, + buf, ARRAY_SIZE(buf)); + if (ret) { + dev_err(&device->dev, "can't get %s\n", name); + return ret; + } + + base = ((u64)buf[0] << 32) | buf[1]; + size = ((u64)buf[2] << 32) | buf[3]; + *addr = devm_ioremap(&device->dev, base, size); + if (!(*addr)) { + dev_err(&device->dev, "error with ioremap\n"); + return -ENOMEM; + } + + return 0; +} + + +static int hisi_pcie_link_up_acpi(struct hisi_pcie *hisi_pcie) +{ + u32 val; + + struct acpi_pci_root *root; + struct acpi_device *device; + union acpi_object *obj; + + root = hisi_pcie->root; + device = root->device; + obj = acpi_evaluate_dsm(device->handle, + hisi_pcie_acpi_dsm_uuid, 0, + GET_PCIE_LINK_STATUS, NULL); + + if (!obj || obj->type != ACPI_TYPE_INTEGER) { + dev_err(&device->dev, "can't get link status from _DSM\n"); + return 0; + } + val = obj->integer.value; + + return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); + +} + +static struct pcie_soc_ops acpi_ops = { + &hisi_pcie_link_up_acpi +}; + +/* + * Retrieve rc_dbi base and size from _DSD + * Name (_DSD, Package () { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + * Package () { + * Package () {"rc-dbi", Package () { 0x0, 0xb0080000, 0x0, 0x10000 }}, + * } + * }) + */ +static int hisi_pcie_init(struct acpi_pci_root *root) +{ + struct hisi_pcie *pcie; + int ret; + struct acpi_device *device; + + device = root->device; + pcie = devm_kzalloc(&device->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + ret = hisi_pcie_get_addr(root, "rc-dbi", &pcie->reg_base); + if (ret) { + dev_err(&device->dev, "can't get rc-dbi\n"); + return ret; + } + + pcie->pp.dbi_base = pcie->reg_base; + pcie->pp.root_bus_nr = root->secondary.start; + pcie->pp.ops = &hisi_pcie_host_ops; + pcie->root = root; + pcie->soc_ops = &acpi_ops; + root->sysdata = &pcie->pp; + return 0; +} + +static int hisi_pcie_match(struct pci_mcfg_fixup *fixup, + struct acpi_pci_root *root) +{ + int ret; + struct acpi_device *device; + + device = root->device; + ret = acpi_match_device_ids(device, hisi_pcie_ids); + if (ret) + return 0; + + ret = hisi_pcie_init(root); + if (ret) + dev_warn(&device->dev, "hisi pcie init fail\n"); + + dw_pcie_ops.map_bus = pci_mcfg_dev_base; + + return 1; +} + +DECLARE_ACPI_MCFG_FIXUP(NULL, hisi_pcie_match, &dw_pcie_ops, + PCI_MCFG_DOMAIN_ANY, PCI_MCFG_BUS_ANY); diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index 1e45869..d7867cf 100644 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -23,8 +23,6 @@ #include "pcie-designware.h" #include "pcie-hisi.h" -#define PCIE_LTSSM_LINKUP_STATE 0x11 -#define PCIE_LTSSM_STATE_MASK 0x3F #define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818 #define PCIE_HIP06_CTRL_OFF 0x1000 #define PCIE_SYS_STATE4 0x31c diff --git a/drivers/pci/host/pcie-hisi.h b/drivers/pci/host/pcie-hisi.h index f64249d..396deb2 100644 --- a/drivers/pci/host/pcie-hisi.h +++ b/drivers/pci/host/pcie-hisi.h @@ -15,6 +15,9 @@ #define PCIE_HISI_H_ struct hisi_pcie { +#ifdef CONFIG_PCI_HISI_ACPI + struct acpi_pci_root *root; +#endif /* CONFIG_ACPI_HOST_GENERIC */ struct regmap *subctrl; void __iomem *reg_base; u32 port_id; @@ -41,4 +44,7 @@ static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg) extern struct pcie_host_ops hisi_pcie_host_ops; +#define PCIE_LTSSM_LINKUP_STATE 0x11 +#define PCIE_LTSSM_STATE_MASK 0x3F + #endif /* PCIE_HISI_H_ */