From patchwork Thu Feb 4 11:37:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 61172 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp396984lbl; Thu, 4 Feb 2016 03:23:30 -0800 (PST) X-Received: by 10.66.166.73 with SMTP id ze9mr9918067pab.67.1454585010404; Thu, 04 Feb 2016 03:23:30 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r82si16113794pfa.214.2016.02.04.03.23.30; Thu, 04 Feb 2016 03:23:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965396AbcBDLX1 (ORCPT + 30 others); Thu, 4 Feb 2016 06:23:27 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:16383 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933238AbcBDLXS (ORCPT ); Thu, 4 Feb 2016 06:23:18 -0500 Received: from 172.24.1.47 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.47]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DED57514; Thu, 04 Feb 2016 19:22:56 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 4 Feb 2016 19:22:47 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH 3/4] PCI: hisi: Make the HiSilicon PCIe host controller ECAM compliant Date: Thu, 4 Feb 2016 19:37:39 +0800 Message-ID: <1454585860-60709-4-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> References: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.56B33491.02B9, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ba75e2fb0783cc69d6629d7738357f9d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni This patch modifies the current Hip05/Hip06 PCIe host controller driver to make it ECAM compliant. This is needed in preparation for the ACPI based driver to allow both DT and ACPI drivers to use the same BIOS (that configure the Designware iATUs). Signed-off-by: Gabriele Paoloni Signed-off-by: Dongdong Liu --- .../devicetree/bindings/pci/hisilicon-pcie.txt | 4 ++-- drivers/pci/host/pcie-hisi-common.c | 15 +++++++++++++++ drivers/pci/host/pcie-hisi.c | 22 ++++++++++++++++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index b721bea..5c1bad0 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -23,8 +23,8 @@ Optional properties: Hip05 Example (note that Hip06 is the same except compatible): pcie@0xb0080000 { compatible = "hisilicon,hip05-pcie", "snps,dw-pcie"; - reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>; - reg-names = "rc_dbi", "config"; + reg = <0 0xb0080000 0 0x10000>, <0x220 0x00100000 0 0x0f00000>; + reg-names = "rc_dbi", "ecam-cfg"; bus-range = <0 15>; msi-parent = <&its_pcie>; #address-cells = <3>; diff --git a/drivers/pci/host/pcie-hisi-common.c b/drivers/pci/host/pcie-hisi-common.c index ff93293..cbfb6c4 100644 --- a/drivers/pci/host/pcie-hisi-common.c +++ b/drivers/pci/host/pcie-hisi-common.c @@ -23,6 +23,19 @@ #include "pcie-hisi.h" /* HipXX PCIe host only supports 32-bit config access */ +static int hisi_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *value) +{ + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int hisi_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 value) +{ + return pci_generic_config_write(bus, devfn, where, size, value); +} + +/* HipXX PCIe host only supports 32-bit config access */ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, u32 *val) { @@ -82,6 +95,8 @@ static int hisi_pcie_link_up(struct pcie_port *pp) } struct pcie_host_ops hisi_pcie_host_ops = { + .rd_other_conf = hisi_rd_other_conf, + .wr_other_conf = hisi_wr_other_conf, .rd_own_conf = hisi_pcie_cfg_read, .wr_own_conf = hisi_pcie_cfg_write, .link_up = hisi_pcie_link_up, diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index 552ebfc..1e45869 100644 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -29,6 +29,18 @@ #define PCIE_HIP06_CTRL_OFF 0x1000 #define PCIE_SYS_STATE4 0x31c +static void __iomem *hisi_pci_map_cfg_bus_cam(struct pci_bus *bus, + unsigned int devfn, + int where) +{ + void __iomem *addr; + struct pcie_port *pp = bus->sysdata; + + addr = pp->va_cfg1_base + where; + + return addr; +} + static int hisi_add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) { @@ -48,6 +60,8 @@ static int hisi_add_pcie_port(struct pcie_port *pp, pp->ops = &hisi_pcie_host_ops; + dw_pcie_ops.map_bus = hisi_pci_map_cfg_bus_cam; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(&pdev->dev, "failed to initialize host\n"); @@ -93,6 +107,14 @@ static int hisi_pcie_probe(struct platform_device *pdev) hisi_pcie->pp.dbi_base = hisi_pcie->reg_base; + reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam-cfg"); + hisi_pcie->pp.va_cfg0_base = devm_ioremap_resource(&pdev->dev, reg); + if (IS_ERR(hisi_pcie->pp.va_cfg0_base)) { + dev_err(pp->dev, "cannot get ecam-cfg\n"); + return PTR_ERR(hisi_pcie->pp.va_cfg0_base); + } + hisi_pcie->pp.va_cfg1_base = hisi_pcie->pp.va_cfg0_base; + ret = hisi_add_pcie_port(pp, pdev); if (ret) return ret;