From patchwork Thu Feb 4 11:37:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 61173 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp397037lbl; Thu, 4 Feb 2016 03:23:38 -0800 (PST) X-Received: by 10.66.63.104 with SMTP id f8mr10116137pas.41.1454585018113; Thu, 04 Feb 2016 03:23:38 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 82si16194272pfn.23.2016.02.04.03.23.37; Thu, 04 Feb 2016 03:23:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965591AbcBDLXd (ORCPT + 30 others); Thu, 4 Feb 2016 06:23:33 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:16397 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933828AbcBDLX1 (ORCPT ); Thu, 4 Feb 2016 06:23:27 -0500 Received: from 172.24.1.47 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.47]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DED57513; Thu, 04 Feb 2016 19:22:55 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 4 Feb 2016 19:22:46 +0800 From: Gabriele Paoloni To: , , , , , , , , CC: , , , , , , , , Subject: [RFC PATCH 1/4] PCI: Designware: Add support for ACPI based controllers Date: Thu, 4 Feb 2016 19:37:37 +0800 Message-ID: <1454585860-60709-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> References: <1454585860-60709-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.56B33491.0176, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 611b805a53be07521fb64ed3fb6f9a7d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni This patch reworks the current Designware framework to enable ACPI based controllers. Signed-off-by: Gabriele Paoloni Signed-off-by: Dongdong Liu --- drivers/pci/host/pcie-designware.c | 39 +++++++++++++++++++++++++++++++++----- drivers/pci/host/pcie-designware.h | 1 + 2 files changed, 35 insertions(+), 5 deletions(-) -- 1.9.1 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 02a7452..4ced20d 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -11,6 +11,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -46,7 +48,6 @@ #define PCIE_MSI_INTR0_ENABLE 0x828 #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 - #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) @@ -69,7 +70,7 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C -static struct pci_ops dw_pcie_ops; +struct pci_ops dw_pcie_ops; int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) { @@ -657,8 +658,22 @@ static int dw_pcie_valid_config(struct pcie_port *pp, static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus->sysdata; int ret; + struct pcie_port *pp; + struct pci_bus *bridge_bus; + + for (bridge_bus = bus; bridge_bus->parent; + bridge_bus = bridge_bus->parent) + ; + + if (has_acpi_companion(bridge_bus->bridge)) { +#ifdef CONFIG_ACPI_PCI_HOST_GENERIC + struct acpi_pci_root *root = bus->sysdata; + + pp = root->sysdata; +#endif /* CONFIG_ACPI_PCI_HOST_GENERIC */ + } else + pp = bus->sysdata; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { *val = 0xffffffff; @@ -681,8 +696,22 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus->sysdata; int ret; + struct pcie_port *pp; + struct pci_bus *bridge_bus; + + for (bridge_bus = bus; bridge_bus->parent; + bridge_bus = bridge_bus->parent) + ; + + if (has_acpi_companion(bridge_bus->bridge)) { +#ifdef CONFIG_ACPI_PCI_HOST_GENERIC + struct acpi_pci_root *root = bus->sysdata; + + pp = root->sysdata; +#endif /* CONFIG_ACPI_PCI_HOST_GENERIC */ + } else + pp = bus->sysdata; if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) return PCIBIOS_DEVICE_NOT_FOUND; @@ -700,7 +729,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, return ret; } -static struct pci_ops dw_pcie_ops = { +struct pci_ops dw_pcie_ops = { .read = dw_pcie_rd_conf, .write = dw_pcie_wr_conf, }; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 2356d29..fd27fa4 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -80,4 +80,5 @@ int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +extern struct pci_ops dw_pcie_ops; #endif /* _PCIE_DESIGNWARE_H */