From patchwork Wed Feb 3 18:39:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 61124 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp13417lbl; Wed, 3 Feb 2016 10:40:13 -0800 (PST) X-Received: by 10.98.93.195 with SMTP id n64mr4576766pfj.67.1454524804133; Wed, 03 Feb 2016 10:40:04 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 127si10793086pfa.4.2016.02.03.10.40.03; Wed, 03 Feb 2016 10:40:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dkim=pass header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933763AbcBCSj4 (ORCPT + 30 others); Wed, 3 Feb 2016 13:39:56 -0500 Received: from mail-pf0-f173.google.com ([209.85.192.173]:33766 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965860AbcBCSjx (ORCPT ); Wed, 3 Feb 2016 13:39:53 -0500 Received: by mail-pf0-f173.google.com with SMTP id w123so18164660pfb.0 for ; Wed, 03 Feb 2016 10:39:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7fG+FHuY03PZVTmX9KhtdpL8xC+NWsm5cngx2mcwMJs=; b=VHXhSq7aCkNyIcN0WnPHN28aLrsSiqt6ubLWbfHmTZO5VIxKPui/Qn1bCk7RA9pGXn vUF51+sMFPpzess+P1tyIZEDRxm7asSz5XL7Mi2K4B8YpUg/5wlZV4xIh7Qhooai9gie ZSdSOmG/shxoNYxAw77cCh1HtxiGlfAlmJI5Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7fG+FHuY03PZVTmX9KhtdpL8xC+NWsm5cngx2mcwMJs=; b=Gw4ramss+deFFh2Y6+3ecg4qQyhqsKeoyFnk7ll8IByx+0ycLUzGDjJbgWrHGjjtKJ 99gxUTYWcpw+ip6fN6c+L3ohkHPFOFUKdrpTAR25qid2V2M97s81vgBfpEWW/VjbtUm9 RvscYXstyHgkCzeu26BJ/gkiUIaZIdDEAq0mhY5WtKmWKAPUW1VClwXgpkzUw/1Z4CN/ fKNdSi6l2XReehK8vpvuX+yKS/qFpa20gyDoVg8J5UI1u1Q/dgVqfIgIJIIgREnms7oH 373dj6xcTDLQ7IMCjqxu/pGC506Kl2it4q6UlB1QpmCXYTIohDOdE27YMXp7SFZFvoS7 WPtg== X-Gm-Message-State: AG10YOQsAifQbrTV/v8msV7S3iBUC3hFjcfnA77EUlMGFFNMc8xdePoXfizU2rRMXEsxH+S6 X-Received: by 10.98.72.133 with SMTP id q5mr4623544pfi.166.1454524792626; Wed, 03 Feb 2016 10:39:52 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xa9sm11369704pab.44.2016.02.03.10.39.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Feb 2016 10:39:52 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, zhang.chunyan@linaro.org, mike.leach@arm.com, alexander.shishkin@linux.intel.com, tor@ti.com Subject: [PATCH V9 10/18] coresight: etm3x: changing default trace configuration Date: Wed, 3 Feb 2016 11:39:08 -0700 Message-Id: <1454524756-10628-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454524756-10628-1-git-send-email-mathieu.poirier@linaro.org> References: <1454524756-10628-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier to narrow down if needed. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 29 ++++++++++++--------------- 2 files changed, 15 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index 5b29d5540fe5..44585d4adb26 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -146,6 +146,7 @@ * @startstop_ctrl: setting for register ETMTSSCR. * @enable_event: setting for register ETMTEEVR. * @enable_ctrl1: setting for register ETMTECR1. + * @enable_ctrl2: setting for register ETMTECR2. * @fifofull_level: setting for register ETMFFLR. * @addr_idx: index for the address comparator selection. * @addr_val: value for address comparator register. @@ -179,6 +180,7 @@ struct etm_config { u32 startstop_ctrl; u32 enable_event; u32 enable_ctrl1; + u32 enable_ctrl2; u32 fifofull_level; u8 addr_idx; u32 addr_val[ETM_MAX_ADDR_CMP]; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 447459969cb5..92139674bea4 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -579,26 +579,23 @@ static void etm_init_arch_data(void *info) static void etm_init_default_data(struct etm_config *config) { - u32 flags = (1 << 0 | /* instruction execute*/ - 3 << 3 | /* ARM instruction */ - 0 << 5 | /* No data value comparison */ - 0 << 7 | /* No exact mach */ - 0 << 8 | /* Ignore context ID */ - 0 << 10); /* Security ignored */ - if (WARN_ON_ONCE(!config)) return; - config->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN); - config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; - config->addr_val[0] = (u32) _stext; - config->addr_val[1] = (u32) _etext; - config->addr_acctype[0] = flags; - config->addr_acctype[1] = flags; - config->addr_type[0] = ETM_ADDR_TYPE_RANGE; - config->addr_type[1] = ETM_ADDR_TYPE_RANGE; - etm_set_default(config); + + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; } static void etm_init_trace_id(struct etm_drvdata *drvdata)